公开(公告)号：US10084048B2

公开(公告)日：2018-09-25

申请号：US14704123

申请日：2015-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda

IPC: H01L29/24 ,  H01L29/786 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/24 ,  H01L27/0886 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with favorable electrical characteristics is provided. Alternatively, a semiconductor device with a high on-state current is provided. Alternatively, a semiconductor device that is suitable for miniaturization is provided. A semiconductor device includes an oxide semiconductor, an insulating film, a gate insulating film, and a gate electrode. The oxide semiconductor includes a first portion and a second portion over the first portion. The insulating film includes a region in contact with a side surface of the first portion. The gate electrode includes a region that covers the second portion with the gate insulating film provided therebetween.

公开(公告)号：US09871143B2

公开(公告)日：2018-01-16

申请号：US14657195

申请日：2015-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Kosei Noda

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/41 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/66969

Abstract: A semiconductor device that is suitable for miniaturization. A method for manufacturing a semiconductor device includes the steps of forming a semiconductor, forming a first conductor over the semiconductor, performing a second process on the first conductor so as to form a conductor according to a first pattern, forming a first insulator over the conductor having the first pattern, forming an opening in the first insulator, performing a third process on the conductor having the first pattern in the opening so as to form a first electrode and a second electrode and to expose the semiconductor, forming a second insulator over the first insulator, an inner wall of the opening, and an exposed portion of the semiconductor, forming a second conductor over the second insulator, and performing a fourth process on the second conductor so as to form a third electrode.

公开(公告)号：US09812544B2

公开(公告)日：2017-11-07

申请号：US14935553

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Hitomi Sato ,  Yuhei Sato

IPC: H01L29/49 ,  H01L27/12 ,  H01L29/786 ,  H01L21/28 ,  H01L21/288 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/28088 ,  H01L21/288 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/7869

Abstract: To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured.

公开(公告)号：US09793383B2

公开(公告)日：2017-10-17

申请号：US15063883

申请日：2016-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda ,  Toshinari Sasaki

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/04 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/477 ,  H01L21/02 ,  H01L21/465 ,  H01L21/66 ,  H01L29/40

CPC classification number: H01L29/66969 ,  H01L21/02164 ,  H01L21/465 ,  H01L21/477 ,  H01L22/10 ,  H01L29/401 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/7869

Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.

公开(公告)号：US09735280B2

公开(公告)日：2017-08-15

申请号：US13777074

申请日：2013-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda ,  Suzunosuke Hiraishi

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696

Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.

公开(公告)号：US09722092B2

公开(公告)日：2017-08-01

申请号：US15050895

申请日：2016-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66818 ,  H01L29/78603 ,  H01L29/78696

Abstract: To provide a transistor with favorable electrical characteristics. A semiconductor device includes a first insulator over a substrate; a first metal oxide over the first insulator; a second metal oxide over the first metal oxide; a first conductor and a second conductor over the second metal oxide; a third metal oxide over the second metal oxide, the first conductor, and the second conductor; a second insulator over the third metal oxide; and a third conductor over the second insulator. The second metal oxide includes a region in contact with a top surface of the first metal oxide and regions in contact with side surfaces of the first metal oxide. The second metal oxide includes channel formation regions.

公开(公告)号：US09608007B2

公开(公告)日：2017-03-28

申请号：US15063664

申请日：2016-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/00 ,  H01L27/00 ,  H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

公开(公告)号：US20170054034A1

公开(公告)日：2017-02-23

申请号：US15249570

申请日：2016-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L29/786 ,  H02M3/158 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H02M3/073 ,  H02M3/158

Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.

Abstract translation: 晶体管包括栅极，源极和漏极，栅极电连接到源极或漏极，第一信号被输入到源极和漏极中的一个，以及载流子浓度为5× 1014 / cm3以下用于沟道形成层。 电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且作为时钟信号的第二信号被输入到第二电极。 第一信号的电压被升高或降低以获得通过晶体管的源极和漏极中的另一个输出作为输出信号的第三信号。

公开(公告)号：US09564534B2

公开(公告)日：2017-02-07

申请号：US14588657

申请日：2015-01-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi Tsubuku ,  Kosei Noda

IPC: H01L29/12 ,  H01L27/15 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/156

Abstract: The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.

Abstract translation: 频带尾部状态和带隙中的缺陷尽可能地减小，由此减小了在带隙附近或小于或等于带隙的能量的光吸收。 在这种情况下，不是仅通过优化氧化物半导体膜的制造条件，而是通过使氧化物半导体成为本质上的本征半导体，或者非常接近本征半导体，减少照射光的作用的缺陷和光照射 基本上减少了。 也就是说，即使在以1×1013个光子/ cm 2·sec传递波长为350nm的光的情况下，也可以使用氧化物半导体形成晶体管的沟道区域，其中， 阈值电压的变化小于或等于0.65 V.

公开(公告)号：US20160247929A1

公开(公告)日：2016-08-25

申请号：US15050895

申请日：2016-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66818 ,  H01L29/78603 ,  H01L29/78696

Abstract: To provide a transistor with favorable electrical characteristics. A semiconductor device includes a first insulator over a substrate; a first metal oxide over the first insulator; a second metal oxide over the first metal oxide; a first conductor and a second conductor over the second metal oxide; a third metal oxide over the second metal oxide, the first conductor, and the second conductor; a second insulator over the third metal oxide; and a third conductor over the second insulator. The second metal oxide includes a region in contact with a top surface of the first metal oxide and regions in contact with side surfaces of the first metal oxide. The second metal oxide includes channel formation regions.

Abstract translation: 提供具有良好电气特性的晶体管。 半导体器件包括在衬底上的第一绝缘体; 第一绝缘体上的第一金属氧化物; 第一金属氧化物上的第二金属氧化物; 在第二金属氧化物上的第一导体和第二导体; 第二金属氧化物上的第三金属氧化物，第一导体和第二导体; 在所述第三金属氧化物上的第二绝缘体; 以及在第二绝缘体上的第三导体。 第二金属氧化物包括与第一金属氧化物的顶表面接触的区域和与第一金属氧化物的侧表面接触的区域。 第二金属氧化物包括沟道形成区域。