Abstract:
The present disclosure relates to an image processing device and method that enable suppression of an increase in the amount of coding of a quantization matrix.An image processing device of the present disclosure includes an up-conversion unit configured to up-convert a quantization matrix limited to a size less than or equal to a transmission size that is a maximum size allowed for transmission, from the transmission size to a size that is identical to a block size that is a processing unit of quantization or dequantization. The present disclosure is applicable to, for example, an image processing device for processing image data.
Abstract:
The present invention relates to an image processing device and method that enable generation of a highly precise prediction image using a small amount of control information.A motion compensation circuit 51 specifies a macroblock corresponding to a prediction image in part of reference frames using a motion vector supplied from a prediction mode determination circuit 41, reads an image thereof from a frame memory 19, and extracts it as a motion compensation image. A motion prediction circuit 52 reads, from a frame memory 122, at least one or more of the remaining reference frames, performs motion prediction of the motion compensation image MC0 supplied from the motion compensation circuit 51 in each frame, reads an image of a macroblock that matches or is similar to the motion compensation image MC0 from the frame memory 122, and extracts it as a motion compensation image. The present invention can be applied to, for example, an encoding device and a decoding device.
Abstract:
Region of Interest (ROI) scalability with SHVC is able to be implemented where scalability is used for part of a picture but not the whole picture. Applications of ROI scalability include traffic monitoring, security monitoring and tiled streaming.
Abstract:
An image processing apparatus and a method capable of reducing an amount of codes in encoding or decoding. A type setting unit uses a deblocked pixel value to set a type of a filter which is common between components of Y, Cb, Cr in units of LCUs, and provides the type to a syntax write unit. An offset setting unit uses a deblocked pixel value to set an offset independent for each of components of Y, Cb, Cr in units of LCUs. An SAO control information setting unit provides the offset or a merge flag, which is set by referring to the offset given by the offset setting unit, to the syntax write unit. The present disclosure can be applied to, for example, an image processing apparatus.
Abstract:
The present invention relates to image processing device and method which can suppress block noise. A filter strength determination unit determines the filter strength for every four lines under the control of a control unit. In other words, if a block boundary determination unit has determined to perform filtering, the filter strength determination unit determines at which strength of the strong filter or the weak filter the filtering process is performed, and outputs the determination result to a filter calculation unit. On this occasion, the filter strength determination unit uses the Bs value in the determination formula of the strong filter. For example, in the case of using the Bs value, the threshold of the determination is set in accordance with a linear function of the Bs value from the control unit. The present disclosure can be applied to, for example, an image processing device.
Abstract:
The present disclosure relates to an image processing apparatus and a method capable of reducing an amount of codes in encoding or decoding.A type setting unit uses a deblocked pixel value to set a type of a filter which is common between components of Y, Cb, Cr in units of LCUs, and provides the type to a syntax write unit. An offset setting unit uses a deblocked pixel value to set an offset independent for each of components of Y, Cb, Cr in units of LCUs. An SAO control information setting unit provides the offset or a merge flag, which is set by referring to the offset given by the offset setting unit, to the syntax write unit. The present disclosure can be applied to, for example, an image processing apparatus.
Abstract:
High efficiency video coding (HEVC) enhancements are described for intra-block copying for reducing motion vector (MV) coding redundancy and enhancing in range extensions (RExt) by selecting a default block my predictor. In reducing MV data redundancy, the value of MVx and/or MVy can have a baseline at the width (W), or height (H) of the respective block, whereby fewer bits need to be encoded. One embodiment for enhancing RExt provides an improved selection of a default block vector predictor for the first CU performing intra-block copying in a CTU.
Abstract:
The present disclosure relates to image processing apparatus and method that can prevent a reduction in image quality. Geometry data that is a frame image having arranged thereon a projected image obtained by projecting 3D data representing a three-dimensional structure on a two-dimensional plane and includes a special value indicating occupancy map information in a range is generated. The generated geometry data is encoded. Further, the encoded data on the geometry data is decoded, and a depth value indicating a position of the 3D data and the occupancy map information are extracted from the decoded geometry data. The present disclosure is applicable to, for example, an information processing apparatus, an image processing apparatus, electronic equipment, an information processing method, or a program.
Abstract:
The present disclosure relates to an image decoding device capable of recognizing performance necessary for decoding more accurately and a method. Coded data of image data and decoding load definition information for defining a magnitude of a load of a decoding process of a partial region of an image of the image data are acquired; decoding of the acquired coded data is controlled based on the acquired decoding load definition information; and the acquired coded data is decoded according to the controlling. The present disclosure can be applied to an information processing device such as an image coding device that scalably codes image data or an image decoding device that decodes encoded data obtained by scalably coding image data.
Abstract:
3D data representing a three-dimensional structure is divided into a plurality of pieces and encoded, an obtained plurality of divided bitstreams is multiplexed, and one bitstream including a separator indicating a position of a joint between the divided bitstreams is generated. Furthermore, a separator indicating a position of a joint between divided bitstreams obtained by dividing 3D data representing a three-dimensional structure into a plurality of pieces and encoding the plurality of divided pieces of the 3D data, which is included in a bitstream obtained by multiplexing a plurality of the divided bitstreams, is analyzed, and the bitstream is divided into every divided bitstream on the basis of information included in the analyzed separator, and decoded. Applications of the technology include being implemented in, for example, an information processing apparatus, an image processing apparatus, electronic equipment, an information processing method, a program, or the like.