公开(公告)号：US20170005012A1

公开(公告)日：2017-01-05

申请号：US15238559

申请日：2016-08-16

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John H. Zhang

IPC分类号： H01L21/84 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/02

CPC分类号： H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

摘要： An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

摘要翻译： 公开了一种模拟集成电路，其中短沟道晶体管堆叠在由绝缘层垂直分隔的长沟道晶体管的顶部。 通过这样的设计，可以生产高密度，高功率和高性能的模拟集成电路芯片，其包括彼此间隔足够远的短路和长通道设备，以避免串扰。 在一个实施例中，晶体管是FinFET，并且长沟道器件是多栅极FinFET。 在一个实施例中，将单镶嵌和双镶嵌装置组合在多层集成电路单元中。 小区可以包含短路和长通道设备的各种组合和配置。 可以通过简单地收缩细胞的尺寸并复制与原始细胞相同尺寸足迹的两个或更多个细胞来制造高密度细胞。

公开(公告)号：US09496415B1

公开(公告)日：2016-11-15

申请号：US14956815

申请日：2015-12-02

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L21/8234 ,  H01L27/146 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/49

CPC分类号： H01L29/78693 ,  H01L21/823437 ,  H01L27/14614 ,  H01L29/247 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

摘要翻译： 工艺和翻转的薄膜器件结构通常包括具有由三个面限定的凹形形状的金属栅极。 这些工艺通常包括形成翻转的薄膜器件结构，使得沟道与金属栅极自对准，并且触点可以与牺牲材料自对准。

公开(公告)号：US09466452B1

公开(公告)日：2016-10-11

申请号：US14675359

申请日：2015-03-31

申请人： STMICROELECTRONICS, INC.

发明人： Qing Liu ,  John H. Zhang

IPC分类号： H01H11/00 ,  H01H59/00

CPC分类号： H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

摘要： An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

摘要翻译： 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

公开(公告)号：US09391020B2

公开(公告)日：2016-07-12

申请号：US14314945

申请日：2014-06-25

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

摘要翻译： 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US20160118307A1

公开(公告)日：2016-04-28

申请号：US14986229

申请日：2015-12-31

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417

摘要： Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

摘要翻译： 增强载流子迁移率的方法和装置。 集成电路可以包括两种类型的半导体器件。 第一类型的装置可以包括金属门和以第一方式应变的通道。 第二类型的装置可以包括金属门和以第二方式应变的通道。 这些门可以共同地包括三种或更少的金属材料。 门可以共享相同的金属材料。 在集成电路上形成半导体器件的方法可以包括分别在对应于第一和第二栅极的集成电路的第一和第二区域中沉积第一和第二金属层。

公开(公告)号：US09214429B2

公开(公告)日：2015-12-15

申请号：US14098346

申请日：2013-12-05

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

摘要翻译： 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150228777A1

公开(公告)日：2015-08-13

申请号：US14175308

申请日：2014-02-07

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696

摘要： Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

摘要翻译： 具有部分凹陷栅极的晶体管被​​构造在具有掩埋氧化物层（BOX）的例如FD-SOI和UTBB器件的绝缘体上硅（SOI）半导体晶片上。 外延生长的沟道区域放宽了掺杂源极和漏极配置图的限制。 部分凹入的栅极和升高的外延源极和漏极区域的形成允许晶体管性能的进一步改善和诸如漏极引起的栅极降低（DIBL）和特征亚阈值斜率的控制的短沟道效应的减少。 可以通过先进的过程控制辅助，改变栅极凹槽以使沟道相对于掺杂物分布形成不同的深度。 部分凹入的栅极具有最初形成为与栅极的三侧接触的相关联的高k栅极电介质。 随后去除高k侧壁和置换较低k氮化硅密封剂降低了栅极和源极和漏极区域之间的电容。

公开(公告)号：US20150162278A1

公开(公告)日：2015-06-11

申请号：US14098346

申请日：2013-12-05

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

摘要翻译： 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150102496A1

公开(公告)日：2015-04-16

申请号：US14053531

申请日：2013-10-14

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.

摘要翻译： 通过在电介质层中形成宽的沟槽，在集成电路中形成金属互连。 在沟槽中形成第二电介质材料的绝缘片。 导电插头和金属线形成在鳍的两侧。

公开(公告)号：US08970004B2

公开(公告)日：2015-03-03

申请号：US13725666

申请日：2012-12-21

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L29/00 ,  H01L27/02 ,  H01L21/266

CPC分类号： H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

摘要： A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

摘要翻译： 公开了用于保护集成电路免受静电放电的结二极管阵列。 结二极管集成了各种尺寸和功能的对称和非对称结二极管。 一些结二极管被配置为通过未封装的互连线提供低电压和电流放电，而其它结构二极管被配置为通过封装的互连线提供高电压和电流放电。 结二极管阵列元件包括p-n结二极管和N + / N + +结二极管。 结二极管包括具有定制形状的植入区域。 如果不需要对称和非对称二极管作为结二极管阵列的组件，则阵列配置有任一类型的二极管之间的隔离区域。 一些结二极管阵列包括掩埋氧化物层，以防止掺杂剂扩散到超过选定深度的衬底中。