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    SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS
    91.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS 有权
    包括垂直间隔半导体通道结构和相关方法的半导体器件

    公开(公告)号：US20150108573A1

    公开(公告)日：2015-04-23

    申请号：US14060874

    申请日：2013-10-23

    Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

    Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

    Memory device having multiple dielectric gate stacks and related methods
    92.
    发明授权
    Memory device having multiple dielectric gate stacks and related methods 有权
    具有多个介电栅极堆叠的存储器件及相关方法

    公开(公告)号：US09006816B2

    公开(公告)日：2015-04-14

    申请号：US13852645

    申请日：2013-03-28

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

    IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

    Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

    MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS
    93.
    发明申请
    MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS 有权
    具有第一和第二介质层的多个介电栅极堆叠的存储器件及相关方法

    公开(公告)号：US20140291750A1

    公开(公告)日：2014-10-02

    申请号：US13852720

    申请日：2013-03-28

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Prasanna KHARE ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

    IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

    Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

    Vertical tunneling FinFET
    94.
    发明授权
    Vertical tunneling FinFET 有权

    公开(公告)号：US11515418B2

    公开(公告)日：2022-11-29

    申请号：US16886193

    申请日：2020-05-28

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing Liu ,  John H. Zhang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/737 ,  H01L27/092 ,  H01L29/739 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

    Dual width FinFET
    96.
    发明授权
    Dual width FinFET 有权

    公开(公告)号：US10886386B2

    公开(公告)日：2021-01-05

    申请号：US15806160

    申请日：2017-11-07

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing Liu

    IPC: H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

    Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

    Integrated cantilever switch
    97.
    发明授权
    Integrated cantilever switch 有权

    公开(公告)号：US10861984B2

    公开(公告)日：2020-12-08

    申请号：US16564860

    申请日：2019-09-09

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  John H. Zhang

    IPC: H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

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