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1.发明授权Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods 有权具有具有第一和第二介电层的多个介电栅极堆叠的存储器件和相关方法公开(公告)号：US08860123B1
公开(公告)日：2014-10-14
申请号：US13852720
申请日：2013-03-28
发明人： Prasanna Khare , Stephane Allegret-Maret , Nicolas Loubet , Qing Liu , Hemanth Jagannathan , Lisa Edge , Kangguo Cheng , Bruce Doris
IPC分类号： H01L29/792 , H01L21/8238 , H01L29/423 , H01L29/66
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
摘要翻译： 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。
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2.发明申请公开(公告)号：US20140291749A1
公开(公告)日：2014-10-02
申请号：US13852645
申请日：2013-03-28
发明人： Prasanna KHARE , Stephane Allegret-Maret , Nicolas Loubet , Qing Liu , Hemanth Jagannathan , Lisa Edge , Kangguo Cheng , Bruce Doris
IPC分类号： H01L29/423 , H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
摘要翻译： 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。
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3.发明授权公开(公告)号：US09006816B2
公开(公告)日：2015-04-14
申请号：US13852645
申请日：2013-03-28
发明人： Prasanna Khare , Stephane Allegret-Maret , Nicolas Loubet , Qing Liu , Hemanth Jagannathan , Lisa Edge , Kangguo Cheng , Bruce Doris
IPC分类号： H01L29/792 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/115
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
摘要翻译： 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。
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4.发明申请MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS 有权具有第一和第二介质层的多个介电栅极堆叠的存储器件及相关方法公开(公告)号：US20140291750A1
公开(公告)日：2014-10-02
申请号：US13852720
申请日：2013-03-28
发明人： Prasanna KHARE , Stephane Allegret-Maret , Nicolas Loubet , Qing Liu , Hemanth Jagannathan , Lisa Edge , Kangguo Cheng , Bruce Doris
IPC分类号： H01L29/423 , H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
摘要翻译： 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。
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公开(公告)号：US11973125B2
公开(公告)日：2024-04-30
申请号：US17586396
申请日：2022-01-27
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/823431 , H01L21/823468 , H01L29/785
摘要： Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.
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公开(公告)号：US20240021609A1
公开(公告)日：2024-01-18
申请号：US17812744
申请日：2022-07-15
发明人： Ruilong Xie , Hemanth Jagannathan , Kangguo Cheng , Juntao Li
IPC分类号： H01L27/088 , H01L29/417 , H01L29/78 , H01L29/66 , H01L21/8234
CPC分类号： H01L27/088 , H01L29/41741 , H01L29/7827 , H01L29/66666 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L21/823487
摘要： Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.
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公开(公告)号：US20240014208A1
公开(公告)日：2024-01-11
申请号：US17810652
申请日：2022-07-05
IPC分类号： H01L27/088 , H01L29/06 , H01L29/423 , H01L21/8234 , H01L29/66
CPC分类号： H01L27/088 , H01L29/0653 , H01L29/42372 , H01L21/823487 , H01L21/823481 , H01L29/66553 , H01L29/6653 , H01L29/66666 , H01L29/7827
摘要： Embodiments of present invention provide a method of forming a transistor structure. The method includes forming a set of vertical fins on top of a substrate; forming a conformal spacer lining the set of vertical fins and the substrate; forming sidewall spacers next to vertical portions of the conformal spacer; removing portions of the conformal spacer on top of the substrate and between the sidewall spacers; indenting the conformal spacer vertically between the sidewall spacers and the substrate to create openings; forming bottom spacers in the openings; and forming a shallow-trench-isolation (STI) structure between the bottom spacers. A structure formed thereby is also provided.
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公开(公告)号：US11842998B2
公开(公告)日：2023-12-12
申请号：US16731210
申请日：2019-12-31
IPC分类号： H01L27/092 , H01L29/165 , H01L29/161 , H01L21/8238 , H01L21/02 , H01L21/324 , H01L29/10 , H01L29/78 , H01L29/66
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823885 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.
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9.发明公开公开(公告)号：US20230154801A1
公开(公告)日：2023-05-18
申请号：US18093932
申请日：2023-01-06
发明人： Heng Wu , Ruilong Xie , Su Chen Fan , Jay William Strane , Hemanth Jagannathan
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/06 , H01L27/092 , H01L21/265 , H01L29/66
CPC分类号： H01L21/823814 , H01L29/7827 , H01L29/0653 , H01L27/092 , H01L21/265 , H01L21/823885 , H01L29/6656
摘要： A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.
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10.发明授权公开(公告)号：US11615990B2
公开(公告)日：2023-03-28
申请号：US16828619
申请日：2020-03-24
发明人： Heng Wu , Ruilong Xie , Su Chen Fan , Jay William Strane , Hemanth Jagannathan
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/06 , H01L21/265 , H01L29/66
摘要： A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.
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