公开(公告)号：US20070120201A1

公开(公告)日：2007-05-31

申请号：US11598646

申请日：2006-11-14

申请人： Hitoshi Yamaguchi ,  Jun Sakakibara

发明人： Hitoshi Yamaguchi ,  Jun Sakakibara

IPC分类号： H01L29/76

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.

摘要翻译： 具有超结MOS晶体管的半导体器件包括：半导体衬底; 在所述基板上的第一半导体层; 在所述第一半导体层上的第二半导体层; 在第二半导体层的第一表面部分上的沟道形成区; 在所述沟道形成区域的第一表面部分上的源极区域; 在所述沟道形成区域的第二表面部分上的源极接触区域; 在沟道形成区域的第三表面部分上的栅电极; 源极区域和源极接触区域上的源极电极; 位于衬底背面的漏电极; 以及在所述第二半导体层的第二表面部分上的阳极电极。 阳极电极提供肖特基势垒二极管。

公开(公告)号：US20060275980A1

公开(公告)日：2006-12-07

申请号：US11434124

申请日：2006-05-16

申请人： Jun Sakakibara ,  Hitoshi Yamaguchi ,  Naohiro Suzuki

发明人： Jun Sakakibara ,  Hitoshi Yamaguchi ,  Naohiro Suzuki

IPC分类号： H01L21/8242 ,  H01L29/76

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/7818

摘要： A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein the epitaxial semiconductor layer is disposed in the first trench. The first trench includes an inner wall as an interface between the semiconductor substrate and the epitaxial semiconductor layer so that the interface provides a PN junction. The first trench has an aspect ratio equal to or larger than 1.

公开(公告)号：US20060255411A1

公开(公告)日：2006-11-16

申请号：US11415228

申请日：2006-05-02

申请人： Naohiro Suzuki ,  Hitoshi Yamaguchi

发明人： Naohiro Suzuki ,  Hitoshi Yamaguchi

IPC分类号： H01L23/62

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/7818 ,  H01L29/7825 ,  H01L29/7835

摘要： A semiconductor device includes: a MOS transistor; a protection diode; and a semiconductor substrate. The MOS transistor and the protection diode are disposed in the semiconductor substrate. The drain of the MOS transistor is connected to the cathode of the protection diode. The source of the MOS transistor is connected to the anode of the protection diode. The MOS transistor has a withstand voltage defined as VT. The protection diode has a withstand voltage defined as VD, a parasitic resistance defined as RD, and a maximum current defined as IRmax. They satisfy a relationship of VT>VD+IRmax×RD. The maximum current of IRmax is equal to or larger than 45 Amperes.

摘要翻译： 半导体器件包括：MOS晶体管; 保护二极管; 和半导体衬底。 MOS晶体管和保护二极管设置在半导体衬底中。 MOS晶体管的漏极连接到保护二极管的阴极。 MOS晶体管的源极连接到保护二极管的阳极。 MOS晶体管具有被定义为V T T的耐受电压。 保护二极管具有定义为V SUB的耐受电压，定义为R D D的寄生电阻，以及定义为I Rmax的最大电流。 它们满足V V + D + I Rmax×R×D 的关系。 I Rmax 的最大电流等于或大于45安培。

公开(公告)号：US20050230747A1

公开(公告)日：2005-10-20

申请号：US11156451

申请日：2005-06-21

申请人： Naohiro Suzuki ,  Jun Sakakibara ,  Yoshitaka Noda ,  Hitoshi Yamaguchi

发明人： Naohiro Suzuki ,  Jun Sakakibara ,  Yoshitaka Noda ,  Hitoshi Yamaguchi

IPC分类号： H01L29/41 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/732 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/7825

摘要： A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.

摘要翻译： 半导体器件包括在N - 硅层。 在主表面的表层部分，在包括漏极N + SUP区域的区域中，N阱区形成得比漏极N + + SUP区域深，并与之接触 与基地区P。 形成沟槽，以从源极N +区域的漏极N + SUP区域的方向穿过基极P区域作为平面结构。 栅极电极通过沟槽内部的栅极绝缘膜形成。

公开(公告)号：US06781201B2

公开(公告)日：2004-08-24

申请号：US10621488

申请日：2003-07-18

申请人： Hitoshi Yamaguchi

发明人： Hitoshi Yamaguchi

IPC分类号： H01L2978

CPC分类号： H01L29/7816 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7801 ,  H01L29/7813 ,  H01L29/7823

摘要： First and second trenches are formed on an n+ type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n− type epitaxial film, a p type epitaxial film, and an n+ type epitaxial film are deposited on the substrate and in the trenches, and then flattening is performed. As a result, an n− type region is provided in the second trench of the peripheral device formation region. Then, a p type well layer is formed in the n− type region by ion-implantation. Accordingly, a power MOSFET and a peripheral device can been formed at the power MOSFET formation region and the peripheral device formation region easily.

摘要翻译： 第一和第二沟槽分别在功率MOSFET形成区域和外围器件形成区域的n +型衬底上形成。 在衬底上和沟槽中沉积n型外延膜，p型外延膜和n +型外延膜，然后进行平坦化。 结果，在外围器件形成区域的第二沟槽中提供n +型区域。 然后，通过离子注入在n +型区域中形成p型阱层。 因此，能够容易地在功率MOSFET形成区域和外围器件形成区域形成功率MOSFET和外围器件。

公开(公告)号：US06753379B1

公开(公告)日：2004-06-22

申请号：US10111113

申请日：2002-04-19

申请人： Kohichiro Kawate ,  Yorinobo Takamatsu ,  Hitoshi Yamaguchi ,  Akito Muramatsu

发明人： Kohichiro Kawate ,  Yorinobo Takamatsu ,  Hitoshi Yamaguchi ,  Akito Muramatsu

IPC分类号： C08L2518

CPC分类号： C09J133/062 ,  C08L67/04 ,  C08L2666/18

摘要： The present invention provides thermally activated adhesive compositions comprising polymer and polyester wherein the adhesive polymer comprises a polymer having hydroxyl and phenyl groups and adhesive films made from the adhesive compositions.

摘要翻译： 本发明提供了包含聚合物和聚酯的热活化粘合剂组合物，其中粘合剂聚合物包含具有羟基和苯基的聚合物以及由粘合剂组合物制成的粘合剂膜。

公开(公告)号：US06525375B1

公开(公告)日：2003-02-25

申请号：US09688154

申请日：2000-10-16

申请人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

发明人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7835

摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

公开(公告)号：US06258039B1

公开(公告)日：2001-07-10

申请号：US09381653

申请日：1999-09-20

申请人： Mineo Okamoto ,  Hitoshi Yamaguchi ,  Yoshikazu Shirane ,  Kenji Demura

发明人： Mineo Okamoto ,  Hitoshi Yamaguchi ,  Yoshikazu Shirane ,  Kenji Demura

IPC分类号： A61B508

CPC分类号： A62B9/00

摘要： The present invention relates to a respiratory gas consumption monitoring method and monitoring device that is portable and has high measurement accuracy, for enabling the analysis and prediction of the respiratory behavior of subjects employing a variety of different types of breathing apparatuses in water, etc. Respiratory gas consumption monitoring device (20), for monitoring the respiratory gas consumption of the user of a breathing apparatus (1) in which a respiratory gas (G) inside a high pressure gas container (2) is reduced in pressure at pressure regulator (4) and supplied to a breathing mask (10), is provided with: a primary pressure sensor (21) for detecting the pressure prior to pressure reduction at pressure regulator (4); a temperature sensor (22) for correction; an environmental pressure sensor (23) for detecting the environmental pressure; an amplifier (24) for amplifying the signals from the aforementioned sensors; an A/D converter (25) for performing analog/digital conversion of the amplified signal; a data logger (26) for recording and storing the analog/digital converted signals; and a display (27) for display. In addition, as needed, a computer (X) for calculating, analyzing, and predicting data may be housed in housing (28), and connected to breathing apparatus (1) by connecting primary pressure sensor (21) to a high pressure opening (8) of pressure regulator (4) using a high pressure hose (29).

摘要翻译： 本发明涉及便携式且具有高测量精度的呼吸气体消耗监测方法和监测装置，用于能够分析和预测在水中使用各种不同类型的呼吸装置的受试者的呼吸行为等。呼吸 气体消耗监测装置（20），用于监测呼吸器（1）的使用者的呼吸气体消耗，其中高压气体容器（2）内的呼吸气体（G）在压力调节器（4） ）并提供给呼吸面罩（10），设置有：用于在压力调节器（4）处检测压力降低之前的压力的主压力传感器（21）;用于校正的温度传感器（22）;环境压力传感器 （23），用于放大来自上述传感器的信号的放大器（24）;用于执行模拟/数字对话的A / D转换器（25） 放大信号的离子;用于记录和存储模拟/数字转换信号的数据记录器（26）; 和显示器（27）。另外，根据需要，用于计算，分析和预测数据的计算机（X）可以容纳在壳体（28）中，并且通过连接主压力传感器（1）连接到呼吸装置（1） 21）使用高压软管（29）连接到压力调节器（4）的高压开口（8）。

公开(公告)号：US5874768A

公开(公告)日：1999-02-23

申请号：US965775

申请日：1997-11-07

申请人： Hitoshi Yamaguchi ,  Hiroaki Himi ,  Seiji Fujino

发明人： Hitoshi Yamaguchi ,  Hiroaki Himi ,  Seiji Fujino

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/36

CPC分类号： H01L29/7824 ,  H01L27/1203 ,  H01L29/66772

摘要： A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.

摘要翻译： 公开了一种以SOI结构形成的高耐压电压半导体器件。 在由半导体衬底上的绝缘体围绕的岛状区域中形成由漂移层，阱阱，源极，栅极和漏极构成的MOS晶体管。 此外，在Si岛区域的底部形成电场缓和层。 电场缓和层是超低浓度的半导体层，例如固有的，因此在p阱和漂移层之间构成虚拟PIN结构。 由于电场减缓层对应于PIN结构的I层，当高电压施加到MOS晶体管时，在电场减缓层内产生耗尽层，高电压分布在整个耗尽层 ，可以得到高的击穿电压。

公开(公告)号：US5261762A

公开(公告)日：1993-11-16

申请号：US899496

申请日：1992-06-16

申请人： Hitoshi Yamaguchi

发明人： Hitoshi Yamaguchi

IPC分类号： E01C19/34 ,  E01C19/35 ,  E02D3/02 ,  E02D3/046 ,  E01C19/00

CPC分类号： E02D3/046 ,  E01C19/35 ,  E02D3/02

摘要： A tamping shoe for a vibration rammer has a plurality of through holes communicating between an under surface and an upper surface. The through holes permit the escape of air trapped between the under surface and a surface being tamped, and thereby reduce the amount and pressure of air compressed under the tamping shoe. This reduces noise pollution produced during tamping. In a preferred embodiment, the through holes are tapered outward in the direction of air flow. Air passing through a through hole in a mount is released through a further through hole bored through a wall of the mount.

摘要翻译： 用于振动夯锤的捣固鞋具有在下表面和上表面之间连通的多个通孔。 通孔允许被捕获在下表面和被夯实的表面之间的空气的逸出，从而减少在捣固鞋下压缩的空气的量和压力。 这样可以减少捣实过程中产生的噪音污染。 在优选实施例中，通孔在空气流动方向上向外锥形。 通过安装件中的通孔的空气通过穿过安装件的壁而穿过的另外的通孔而被释放。