公开(公告)号：US07479430B2

公开(公告)日：2009-01-20

申请号：US12049148

申请日：2008-03-14

申请人： Seiichi Mori

发明人： Seiichi Mori

IPC分类号： H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/511 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less. The inter-insulating layer also may includes a silicon oxide layer serving as a layer contiguous to at least one of the floating gate and the control gate, and having a lower trap density than that of a silicon nitride layer formed by a CVD method.

摘要翻译： 根据本发明的非易失性半导体存储器件具有半导体衬底和具有通过半导体衬底上的隧道绝缘层提供的浮置栅极的存储单元，以及通过所述浮置上的层间绝缘层提供的控制栅极 门。 绝缘层包括与所述浮置栅极相邻的氧化硅层，通过CVD法在氧化硅层上提供的第一氮化硅层和设置在所述第一氮化硅层上并具有较低陷阱密度的第二氮化硅层 比第一氮化硅层的厚度大。 绝缘层可以包括与所述浮置栅极相邻的氧化硅层和沉积在所述氧化硅层上并且具有大约1019 / cm3或更小量级的氢含量的氧化硅层。 绝缘层还可以包括用作与浮动栅极和控制栅极中的至少一个相邻的层的氧化硅层，并且具有比通过CVD方法形成的氮化硅层的陷阱密度低的陷阱密度。

公开(公告)号：US07449745B2

公开(公告)日：2008-11-11

申请号：US11687019

申请日：2007-03-16

申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

公开(公告)号：US07382016B2

公开(公告)日：2008-06-03

申请号：US11292362

申请日：2005-12-02

申请人： Michiharu Matsui ,  Seiichi Mori

发明人： Michiharu Matsui ,  Seiichi Mori

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543

摘要： A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

摘要翻译： 公开了一种半导体器件，其包括形成在半导体衬底中的沟槽型器件隔离区，由隔离区电隔离的半导体有源区，形成为与隔离区自对准的第一电极层和形成在隔离区上的第二电极层 所述第一电极层具有绝缘膜，所述隔离区的顶部位于所述第二电极层的存在的区域中，位于所述第一电极层的顶部以下的第一水平面的上方， 所述有源区域和所述第二电极层不存在的区域处于低于所述第一电平的第二电平，并且所述有源区域的表面在所述第二电极层存在的区域中处于基本相同的水平;以及 在第二电极层不存在的区域。

公开(公告)号：US07348627B2

公开(公告)日：2008-03-25

申请号：US11399657

申请日：2006-04-07

申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气 经由开口部与第一电极层连接。

公开(公告)号：US20060197226A1

公开(公告)日：2006-09-07

申请号：US11399657

申请日：2006-04-07

申请人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气 经由开口部与第一电极层连接。

公开(公告)号：US20060099755A1

公开(公告)日：2006-05-11

申请号：US11258193

申请日：2005-10-26

申请人： Seiichi Mori

发明人： Seiichi Mori

IPC分类号： H01L21/8238

CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

摘要： A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film (22), second-layer polycrystalline silicon film (24) and third-layer polycrystalline silicon film 28, and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.

公开(公告)号：US20060076611A1

公开(公告)日：2006-04-13

申请号：US11292362

申请日：2005-12-02

申请人： Michiharu Matsui ,  Seiichi Mori

发明人： Michiharu Matsui ,  Seiichi Mori

IPC分类号： H01L29/788 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543

摘要： A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

公开(公告)号：US06902976B2

公开(公告)日：2005-06-07

申请号：US10691572

申请日：2003-10-24

申请人： Michiharu Matsui ,  Seiichi Mori

发明人： Michiharu Matsui ,  Seiichi Mori

IPC分类号： H01L21/336 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543

摘要： A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

摘要翻译： 公开了一种半导体器件，其包括形成在半导体衬底中的沟槽型器件隔离区，由隔离区电隔离的半导体有源区，形成为与隔离区自对准的第一电极层和形成在隔离区上的第二电极层 所述第一电极层具有绝缘膜，所述隔离区的顶部位于所述第二电极层的存在的区域中，位于所述第一电极层的顶部以下的第一水平面的上方， 所述有源区域和所述第二电极层不存在的区域处于低于所述第一电平的第二电平，并且所述有源区域的表面在所述第二电极层存在的区域中处于基本相同的水平;以及 在第二电极层不存在的区域。

公开(公告)号：US20050111269A1

公开(公告)日：2005-05-26

申请号：US10661520

申请日：2003-09-15

申请人： Seiichi Mori ,  Shigeru Atsumi

发明人： Seiichi Mori ,  Shigeru Atsumi

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

摘要翻译： 半导体器件至少具有存储单元阵列。 存储单元阵列具有以预定间隔彼此平行地线性延伸的有源区，并且每个包含交替的源极和漏极区，栅电极正交地与源极和漏极区之间的有源区相交，并且每个具有浮置栅极和控制栅极 一个接一个地，第一导体与栅电极平行延伸并且通过源触点连接到相应的源极区，并且通过漏极触点连接到相应的漏区。

公开(公告)号：US20050099847A1

公开(公告)日：2005-05-12

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： G11C16/00 ,  G06K17/00 ,  G06K19/077 ,  G11C11/34 ,  G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.