公开(公告)号：US06222773B1

公开(公告)日：2001-04-24

申请号：US09592661

申请日：2000-06-13

申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

IPC分类号： G11C1600

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

公开(公告)号：US06118697A

公开(公告)日：2000-09-12

申请号：US324775

申请日：1999-06-03

申请人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

发明人： Tooru Tanzawa ,  Nobuaki Otsuka ,  Hironori Banba ,  Shigeru Atsumi ,  Masao Kuriyama ,  Seiichi Mori ,  Seiji Yamada

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/14

摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.

摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。 多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线 并且源极连接到源极线。 行解码器在数据编程时选择多个字线之一。 单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。 当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

公开(公告)号：US20050111269A1

公开(公告)日：2005-05-26

申请号：US10661520

申请日：2003-09-15

申请人： Seiichi Mori ,  Shigeru Atsumi

发明人： Seiichi Mori ,  Shigeru Atsumi

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

摘要翻译： 半导体器件至少具有存储单元阵列。 存储单元阵列具有以预定间隔彼此平行地线性延伸的有源区，并且每个包含交替的源极和漏极区，栅电极正交地与源极和漏极区之间的有源区相交，并且每个具有浮置栅极和控制栅极 一个接一个地，第一导体与栅电极平行延伸并且通过源触点连接到相应的源极区，并且通过漏极触点连接到相应的漏区。

公开(公告)号：US07002203B2

公开(公告)日：2006-02-21

申请号：US10661520

申请日：2003-09-15

申请人： Seiichi Mori ,  Shigeru Atsumi

发明人： Seiichi Mori ,  Shigeru Atsumi

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

公开(公告)号：US06642569B2

公开(公告)日：2003-11-04

申请号：US09956876

申请日：2001-09-21

申请人： Seiichi Mori ,  Shigeru Atsumi

发明人： Seiichi Mori ,  Shigeru Atsumi

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

公开(公告)号：US20110186921A1

公开(公告)日：2011-08-04

申请号：US13085884

申请日：2011-04-13

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

公开(公告)号：US07258096B2

公开(公告)日：2007-08-21

申请号：US11359454

申请日：2006-02-23

申请人： Seiichi Mori ,  Manabu Enari

发明人： Seiichi Mori ,  Manabu Enari

IPC分类号： F01M11/03 ,  F02B75/22

CPC分类号： F01M11/03 ,  F01M2001/1064

摘要： The number of constituent parts for an oil filter fixing system such as a bracket, are reduced, and the oil leaks during filter element exchange are avoided. The oil filter fixing system comprises a V bank of a V type engine, a crankcase fixed with the V bank and an oil filter fixed with the crankcase. A horizontal fixing plane is formed at a part of an outer surface of the crankcase and the oil filter is directly fixed with and hung down from the horizontal plane. Further, the horizontal fixing plane is provided at an outer surface of the crankcase and moreover under a cam fixing portion provided in the crankcase. The oil filter is disposed in a space which is formed by the horizontal fixing plane and a lower vertical side surface of the crankcase.

摘要翻译： 用于诸如支架的油过滤器固定系统的组成部件的数量减少，并且避免在过滤元件更换期间的油泄漏。 油过滤器固定系统包括V型发动机的V组，与V组固定的曲轴箱和固定有曲轴箱的油过滤器。 在曲轴箱的外表面的一部分处形成水平固定平面，并且油滤器直接与水平面固定并悬挂在水平面上。 此外，水平固定平面设置在曲轴箱的外表面处，并且还设置在设置在曲轴箱中的凸轮固定部分下方。 油过滤器设置在由水平固定平面和曲轴箱的下垂直侧面形成的空间中。

公开(公告)号：US20070190727A1

公开(公告)日：2007-08-16

申请号：US11783368

申请日：2007-04-09

申请人： Hiroaki Hazama ,  Seiichi Mori ,  Hirohisa Iizuka ,  Norio Ootani ,  Kazuhito Narita

发明人： Hiroaki Hazama ,  Seiichi Mori ,  Hirohisa Iizuka ,  Norio Ootani ,  Kazuhito Narita

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7881

摘要： A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.

摘要翻译： 一种制造在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件的方法，还包括在半导体衬底中形成用于存储单元的第一阱和用于MOS晶体管的第二阱。

公开(公告)号：US20070057315A1

公开(公告)日：2007-03-15

申请号：US11556299

申请日：2006-11-03

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

公开(公告)号：US07141474B2

公开(公告)日：2006-11-28

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

摘要翻译： 一种制造非易失性半导体存储器的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层和浮置栅极的第一导电层; 沉积栅极间绝缘层; 在所述栅极绝缘层的一部分中形成开口; 通过所述开口在所述栅极间绝缘层上沉积控制栅极电极和所述第一导电层的暴露部分; 以及通过利用所述控制栅电极，所述栅极间绝缘层和所述第一导电层的蚀刻工艺，形成所述存储单元晶体管的栅电极和所述选择晶体管的栅电极，其中所述选择晶体管至少包括一部分 的第一导电层的暴露部分。