公开(公告)号：US09082651B2

公开(公告)日：2015-07-14

申请号：US14040055

申请日：2013-09-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L27/11521 ,  H01L21/28282 ,  H01L21/823456 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

摘要： A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

摘要翻译： 一种器件包括在衬底上的控制栅极结构，在衬底上的存储器栅极结构，其中形成在控制栅极结构和存储器栅极结构之间的电荷存储层，沿着存储器栅极结构的侧壁的第一间隔物，第二 间隔在存储器栅极结构的顶表面上，形成在衬底中并且与存储器栅极结构相邻的第一漏极/源极区域和形成在衬底中并且与控制栅极结构相邻的第二漏极/源极区域。

公开(公告)号：US09048335B2

公开(公告)日：2015-06-02

申请号：US13782720

申请日：2013-03-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Nien Chen ,  Eric Huang ,  Chi-Hsun Hsieh ,  Wei Cheng Wu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28158 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

摘要： An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

摘要翻译： 公开了一种具有多个不同器件栅极配置的集成电路及其制造方法。 形成电路的示例性实施例包括接收具有第一器件区域，第二器件区域和第三器件区域的衬底。 在第一器件区域，第二器件区域和第三器件区域中的每一个的至少一部分上形成第一界面层。 图案化第一界面层以在第三器件区域内限定栅极堆叠。 在第二装置区域的至少一部分上形成第二界面层。 图案化第二界面层以在第二装置区域内限定栅极堆叠。 在第一装置区域的至少一部分上形成第三界面层。 第三界面层限定第一装置区域内的栅极堆叠。

公开(公告)号：US20140291769A1

公开(公告)日：2014-10-02

申请号：US14305407

申请日：2014-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Boa-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L27/092

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成第一栅极结构和第二栅极结构。 第一和第二栅极结构各自包括位于衬底上方的高k电介质层，位于高k电介质层上方的覆盖层，位于覆盖层上方的N型功函数金属层和位于 超过N型功函金属层。 该方法包括在衬底，第一栅极结构和第二栅极结构之上形成层间电介质（ILD）层。 该方法包括抛光ILD层，直到ILD层的表面与第一栅极结构和第二栅极结构的表面基本上共面。 该方法包括用金属栅极替换第二栅极结构的部分。 然后对半导体器件执行硅化处理。

公开(公告)号：US20140252504A1

公开(公告)日：2014-09-11

申请号：US13793220

申请日：2013-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd

发明人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Meng-Fang Hsu ,  Kong-Pin Chang ,  Chia Ming Liang

IPC分类号： H01L29/66 ,  H01L21/76 ,  H01L29/78

CPC分类号： H01L21/76 ,  H01L21/26533 ,  H01L21/2658 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/7834

摘要： A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

摘要翻译： 一种用于制造半导体器件的方法包括接收具有设置在衬底上的隔离特征的硅衬底和邻近隔离特征的阱，其中阱包括第一掺杂剂。 该方法还包括蚀刻凹槽以去除阱的一部分并在凹槽中外延生长硅层（EPI层）以形成沟道，其中沟道包括第二掺杂剂。 该方法还包括在阱和EPI层之间形成阻挡层，阻挡层包括硅碳或氧化硅中的至少一种。 阻挡层可以在通道之前或之后形成。 该方法还包括形成设置在通道上方的栅电极，并在阱中形成源极和漏极。

公开(公告)号：US20140252455A1

公开(公告)日：2014-09-11

申请号：US13792152

申请日：2013-03-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Yi-Ren Chen ,  Ming Zhu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827

摘要： The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.

摘要翻译： 本公开提供了SRAM单元的一个实施例，其包括交叉耦合用于数据存储的第一和第二反相器，每个反相器包括至少一个上拉器件和至少一个下拉器件; 以及配置有两个交叉耦合的反相器的至少两个通过栅极器件。 上拉器件，下拉器件和栅极器件包括隧道场效应晶体管（TFET），其还包括形成在半导体衬底上并具有底部，中间部分和顶部的半导体台面 ; 在底部形成并延伸到半导体衬底中的第一导电类型的漏极; 形成在顶部的第二导电类型的源，第二导电类型与第一导电类型相反; 中间部分的通道，并插入在源极和漏极之间; 以及形成在半导体台面的侧壁上并与沟道接触的栅极。

公开(公告)号：US20140246732A1

公开(公告)日：2014-09-04

申请号：US13782720

申请日：2013-03-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Nien Chen ,  Eric Huang ,  Chi-Hsun Hsieh ,  Wei Cheng Wu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28158 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

摘要： An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

摘要翻译： 公开了一种具有多个不同器件栅极配置的集成电路及其制造方法。 形成电路的示例性实施例包括接收具有第一器件区域，第二器件区域和第三器件区域的衬底。 在第一器件区域，第二器件区域和第三器件区域中的每一个的至少一部分上形成第一界面层。 图案化第一界面层以在第三器件区域内限定栅极堆叠。 在第二装置区域的至少一部分上形成第二界面层。 图案化第二界面层以在第二装置区域内限定栅极堆叠。 在第一装置区域的至少一部分上形成第三界面层。 第三界面层限定第一装置区域内的栅极堆叠。