公开(公告)号：US09831235B2

公开(公告)日：2017-11-28

申请号：US14593473

申请日：2015-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.

公开(公告)号：US20170278755A1

公开(公告)日：2017-09-28

申请号：US15620479

申请日：2017-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/823437 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092

摘要： A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

公开(公告)号：US20160190018A1

公开(公告)日：2016-06-30

申请号：US14975055

申请日：2015-12-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Nien Chen ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Jin-Aun NG ,  Ming Zhu

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L27/06 ,  H01L49/02

CPC分类号： H01L21/823842 ,  H01L21/28158 ,  H01L21/823857 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US20150255352A1

公开(公告)日：2015-09-10

申请号：US14720216

申请日：2015-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/823437 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092

摘要： A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

摘要翻译： 形成半导体结构的方法可以包括：在衬底上形成具有第一厚度的第一介电层; 去除所述第一电介质层的第一部分以暴露所述衬底的第二区域; 在所述衬底的所述第二区域上形成具有第二厚度的第二电介质层; 去除所述第一电介质层的第二部分以暴露所述衬底的第三区域; 在所述基板的第三区域上形成具有第三厚度的第三介电层; 以及在所述衬底的第一区域中形成包括所述第一电介质层的第一多个栅极堆叠，在所述衬底的第二区域中包括所述第二电介质层的第二多个栅极堆叠，以及包括所述第三栅极堆叠的第三多个栅极堆叠 在基板的第三区域中的介电层。

公开(公告)号：US09048335B2

公开(公告)日：2015-06-02

申请号：US13782720

申请日：2013-03-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Nien Chen ,  Eric Huang ,  Chi-Hsun Hsieh ,  Wei Cheng Wu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28158 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

摘要： An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

摘要翻译： 公开了一种具有多个不同器件栅极配置的集成电路及其制造方法。 形成电路的示例性实施例包括接收具有第一器件区域，第二器件区域和第三器件区域的衬底。 在第一器件区域，第二器件区域和第三器件区域中的每一个的至少一部分上形成第一界面层。 图案化第一界面层以在第三器件区域内限定栅极堆叠。 在第二装置区域的至少一部分上形成第二界面层。 图案化第二界面层以在第二装置区域内限定栅极堆叠。 在第一装置区域的至少一部分上形成第三界面层。 第三界面层限定第一装置区域内的栅极堆叠。

公开(公告)号：US20140246732A1

公开(公告)日：2014-09-04

申请号：US13782720

申请日：2013-03-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Nien Chen ,  Eric Huang ,  Chi-Hsun Hsieh ,  Wei Cheng Wu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28158 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

摘要： An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

摘要翻译： 公开了一种具有多个不同器件栅极配置的集成电路及其制造方法。 形成电路的示例性实施例包括接收具有第一器件区域，第二器件区域和第三器件区域的衬底。 在第一器件区域，第二器件区域和第三器件区域中的每一个的至少一部分上形成第一界面层。 图案化第一界面层以在第三器件区域内限定栅极堆叠。 在第二装置区域的至少一部分上形成第二界面层。 图案化第二界面层以在第二装置区域内限定栅极堆叠。 在第一装置区域的至少一部分上形成第三界面层。 第三界面层限定第一装置区域内的栅极堆叠。

公开(公告)号：US20140183648A1

公开(公告)日：2014-07-03

申请号：US13795834

申请日：2013-03-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry-Hak-Lay Chuang ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/823437 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092

摘要： A structure and method of forming the structure is disclosed. According to an embodiment, a structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack.

摘要翻译： 公开了一种形成结构的结构和方法。 根据一个实施例，一种结构包括在衬底的相应三个区域中的三个器件。 第一器件包括第一栅极堆叠，并且第一栅极堆叠包括第一介电层。 第二装置包括第二栅极堆叠，并且第二栅极堆叠包括第二电介质层。 第三器件包括第三栅极堆叠，并且第三栅极堆叠包括第三介电层。 第三电介质层的厚度小于第二电介质层的厚度，第二电介质层的厚度小于第一电介质层的厚度。 第三栅极堆叠的栅极长度与第一栅极堆叠的栅极长度和第二栅极堆叠的栅极长度的量不同。

公开(公告)号：US10276447B2

公开(公告)日：2019-04-30

申请号：US15620479

申请日：2017-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/8234 ,  H01L27/092 ,  H01L21/8238

摘要： A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

公开(公告)号：US09059022B2

公开(公告)日：2015-06-16

申请号：US13795834

申请日：2013-03-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/823437 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092

摘要： A structure and method of forming the structure is disclosed. According to an embodiment, a structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack.

摘要翻译： 公开了一种形成结构的结构和方法。 根据一个实施例，一种结构包括在衬底的相应三个区域中的三个器件。 第一器件包括第一栅极堆叠，并且第一栅极堆叠包括第一介电层。 第二装置包括第二栅极堆叠，并且第二栅极堆叠包括第二电介质层。 第三器件包括第三栅极堆叠，并且第三栅极堆叠包括第三介电层。 第三电介质层的厚度小于第二电介质层的厚度，第二电介质层的厚度小于第一电介质层的厚度。 第三栅极堆叠的栅极长度与第一栅极堆叠的栅极长度和第二栅极堆叠的栅极长度的量不同。

公开(公告)号：US08940596B2

公开(公告)日：2015-01-27

申请号：US14058523

申请日：2013-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/02 ,  H01L21/283 ,  H01L21/48 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.

摘要翻译： 一种方法包括去除结构的栅极层的第一部分。 该结构包括漏极区，源极区和栅极叠层，并且栅极堆叠包括栅极电介质层，直接在栅极介电层上的栅极导电层，以及直接在栅极导电层上的栅极层。 在漏极区域上形成漏极接触区域，在源极区域形成源极接触区域。 导电区域直接形成在栅极导电层上并且邻近栅极层的第二部分。 栅极接触端子形成为与导电区域接触。