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公开(公告)号：US20240324229A1
公开(公告)日：2024-09-26
申请号：US18731454
申请日：2024-06-03
IPC分类号： H10B43/35 , H01L21/033 , H01L21/28 , H01L29/06 , H01L29/423 , H10B43/50
CPC分类号： H10B43/35 , H01L21/0337 , H01L29/0649 , H01L29/40117 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.
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公开(公告)号：US20240290859A1
公开(公告)日：2024-08-29
申请号：US18655397
申请日：2024-05-06
发明人： Wei Cheng Wu , Alexander Kalnitsky , Shih-Hao Lo , Hung-Pin Ko
IPC分类号： H01L29/423 , H01L29/66
CPC分类号： H01L29/42376 , H01L29/66545 , H01L29/66553
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure on a semiconductor substrate. A gate electrode structure is on the gate dielectric structure. The gate electrode structure includes a lower conductive structure and a gate body structure. The gate body structure includes an upper segment over a top surface of the lower conductive structure and a lower segment disposed between opposing inner sidewalls of the lower conductive structure.
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公开(公告)号：US12015029B2
公开(公告)日：2024-06-18
申请号：US18365424
申请日：2023-08-04
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417
CPC分类号： H01L27/0886 , H01L29/0649 , H01L29/41791
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US20230380171A1
公开(公告)日：2023-11-23
申请号：US18364022
申请日：2023-08-02
IPC分类号： H10B43/35 , H01L21/28 , H01L21/033 , H01L29/06 , H01L29/423 , H10B43/50
CPC分类号： H10B43/35 , H01L29/40117 , H01L21/0337 , H01L29/0649 , H01L29/42352 , H10B43/50
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.
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公开(公告)号：US20230170249A1
公开(公告)日：2023-06-01
申请号：US17738290
申请日：2022-05-06
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Chung-Jen Huang , Wen-Tuo Huang , Ya-Chi Hung , Chia-Sheng Lin
IPC分类号： H01L21/762 , H01L21/8234 , H01L23/48 , H01L23/522
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L23/481 , H01L23/5226
摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.
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公开(公告)号：US20220415930A1
公开(公告)日：2022-12-29
申请号：US17572891
申请日：2022-01-11
发明人： Harry-Hak-Lay Chuang , Wen-Tuo Huang , Hsin Fu Lin , Wei Cheng Wu
IPC分类号： H01L27/12 , H01L21/768 , H01L21/762 , H01L23/48
摘要： In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.
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公开(公告)号：US20220285344A1
公开(公告)日：2022-09-08
申请号：US17751958
申请日：2022-05-24
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/417 , H01L29/06
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US20200321238A1
公开(公告)日：2020-10-08
申请号：US16908027
申请日：2020-06-22
发明人： Harry-Hak-Lay Chuang , Bao-Ru Young , Wei Cheng Wu , Meng-Fang Hsu , Kong-Pin Chang , Chia Ming Liang
IPC分类号： H01L21/76 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/762
摘要： A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
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公开(公告)号：US10418361B2
公开(公告)日：2019-09-17
申请号：US15192706
申请日：2016-06-24
发明人： Po-Nien Chen , Bao-Ru Young , Chi-Hsun Hsieh , Harry Hak-Lay Chuang , Wei Cheng Wu , Eric Huang
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/51 , H01L21/28
摘要： An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.
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公开(公告)号：US09929168B2
公开(公告)日：2018-03-27
申请号：US15161766
申请日：2016-05-23
发明人： Wei Cheng Wu , Harry-Hak-Lay Chuang
IPC分类号： H01L27/11568 , H01L21/28 , H01L27/105 , H01L27/11573 , H01L27/11 , H01L21/8234 , H01L29/66 , H01L21/02 , H01L29/51
CPC分类号： H01L27/11568 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/28282 , H01L21/823462 , H01L27/105 , H01L27/1116 , H01L27/11573 , H01L29/513 , H01L29/66545 , H01L29/66833
摘要： A method for forming an embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate is disclosed. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer.
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