公开(公告)号：US10446555B2

公开(公告)日：2019-10-15

申请号：US15691974

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US09806071B2

公开(公告)日：2017-10-31

申请号：US15243787

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L23/48 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

公开(公告)号：US09653393B2

公开(公告)日：2017-05-16

申请号：US14104730

申请日：2013-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Yu Chen ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Hsiang-Jen Tseng

IPC: H01L21/00 ,  H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L23/5226 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line.

公开(公告)号：US20160343656A1

公开(公告)日：2016-11-24

申请号：US15231135

申请日：2016-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L29/40 ,  H01L27/088 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/528 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

Abstract translation: 半导体器件包括具有有源区的衬底，衬底顶表面上的第一栅极结构，在衬底顶表面上的第二栅极结构，第一栅极结构的每个侧壁上的一对第一间隔物， 在所述第二栅极结构的每个侧壁上的一对第二间隔物，至少所述第一栅极结构上的绝缘层，所述有源区上的第一导电特征和所述衬底上的第二导电特征。 此外，第二栅极结构与第一栅极结构相邻，并且第一导电特征的顶表面与第二导电特征的顶表面共面。

公开(公告)号：US20160254194A1

公开(公告)日：2016-09-01

申请号：US15149925

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lee-Chung Lu ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/3205 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/823418 ,  H01L27/0207 ,  H01L27/326 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/4238

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

Abstract translation: 提供集成电路。 集成电路包括设置在第一源极/漏极区域上的第一触点，设置在第二源极/漏极区域上的第二触点，设置在栅极上的多晶硅，插入在第一触点和第二触点之间的多晶硅，第一多晶硅 在有源区内桥接多晶硅和第一接触，以及电耦合到第一多晶硅接触的输出结构。

公开(公告)号：US09425141B2

公开(公告)日：2016-08-23

申请号：US14610294

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract translation: 集成电路包括第一层上的第一层。 第一层包括一组第一行。 第一行各有一个长度和宽度。 第一行的长度大于宽度。 集成电路还包括与第一电平不同的第二电平的第二层。 第二层包括一组第二线。 第二行各有一个长度和一个宽度。 第二行的长度大于宽度。 集成电路还包括被配置为将该组第一线的至少一条第一线与该组第二线的至少一条第二线连接的耦合。 联轴器具有长度和宽度。 该组第二线具有在第一方向上的该组第二线的线之间测量的间距。 第一耦合的长度大于或等于音高。

公开(公告)号：US20160063166A1

公开(公告)日：2016-03-03

申请号：US14473614

申请日：2014-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Yu-Cheng Yeh ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Liang-Yao Lee ,  Jyh-Kang Ting

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract translation: 提供了一种用于电池排设计的贴装基台处理。 在一个实施例中，将第一单元和第二单元放置在第一单元行中，将第三单元和第四单元放置在第二单元行中。 在将电源和接地导轨连接到基础结构的放置通孔进行分析之后，确定是否可以合并或完全除去。 通过合并和去除紧密放置的通孔，可以绕过光刻的物理限制，允许形成更小的结构。

公开(公告)号：US12283586B2

公开(公告)日：2025-04-22

申请号：US17462974

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Ling Chang ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Chia-Tien Wu ,  Jia-Hong Gao

IPC: H01L27/02 ,  G06F30/392 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

公开(公告)号：US12216981B2

公开(公告)日：2025-02-04

申请号：US18448143

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US12159899B2

公开(公告)日：2024-12-03

申请号：US18335162

申请日：2023-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Kuo-Nan Yang

IPC: H01L29/06 ,  H01L27/092

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.