公开(公告)号：US12080588B2

公开(公告)日：2024-09-03

申请号：US18358321

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC: H01L21/74 ,  H01L23/535 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/785 ,  H10B10/12

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US12039247B2

公开(公告)日：2024-07-16

申请号：US17397684

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US11854807B2

公开(公告)日：2023-12-26

申请号：US16806206

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min Hsiao ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Shih-Ming Chang ,  Yung-Sung Yen ,  Yu-Chen Chang

IPC: H01L21/033 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

公开(公告)号：US20230384691A1

公开(公告)日：2023-11-30

申请号：US18361879

申请日：2023-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Yo Jheng ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Chih-Jie Lee ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G03F7/00 ,  G03F1/36

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/705

Abstract: A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

公开(公告)号：US20230377941A1

公开(公告)日：2023-11-23

申请号：US18358321

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC: H01L21/74 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US20230343636A1

公开(公告)日：2023-10-26

申请号：US18344229

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/2633 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76877

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US11610778B2

公开(公告)日：2023-03-21

申请号：US17240692

申请日：2021-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Min Hsiao ,  Chien-Wen Lai ,  Shih-Chun Huang ,  Yung-Sung Yen ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: H01L21/033 ,  H01L27/11

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US11581300B2

公开(公告)日：2023-02-14

申请号：US17092100

申请日：2020-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US11495687B2

公开(公告)日：2022-11-08

申请号：US17001390

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/74 ,  H01L23/538 ,  H01L23/535 ,  H01L29/417

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20220223474A1

公开(公告)日：2022-07-14

申请号：US17705487

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Gun Liu ,  Shih-Ming Chang ,  Hoi-Tou Ng

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.