公开(公告)号：US20120007671A1

公开(公告)日：2012-01-12

申请号：US12681222

申请日：2008-08-29

申请人： Hideki Kumagai ,  Takashi Kumagai

发明人： Hideki Kumagai ,  Takashi Kumagai

IPC分类号： H03F3/68

CPC分类号： H04B1/12 ,  G01V3/12

摘要： An output signal SHS is secondarily amplified by a high-frequency amplifier AMP3 and an output signal SHR is secondarily amplified by an AMP4 for which high-frequency side amplitude reducing means is taken. In this case, the AMP4 has small gain of a high-frequency region and its output SHR-2 is reduced in amplitude. However, a high-frequency noise has a frequency higher than that of a carrier wave SH and the amplitude of a noise NzB becomes smaller. The other output signal SHS is directly amplified by the wideband amplifier AMP3. The width of an SHS-2 and the width of the SHR-2 are adjusted by amplitude adjusting means throughout the whole region and then mutually added by both signals addition amplifying means again so that the amplitude of the output signal SHS is adjusted to the SHR-2, and a predetermined threshold value is set to extract the noises.

摘要翻译： 输出信号SHS被高频放大器AMP3二次放大，并且输出信号SHR由被采用高频侧振幅降低装置的AMP4二次放大。 在这种情况下，AMP4具有高频区域的小增益，并且其输出SHR-2的振幅减小。 然而，高频噪声的频率高于载波SH的频率，并且噪声的振幅NzB变小。 另一个输出信号SHS由宽带放大器AMP3直接放大。 SHS-2的宽度和SHR-2的宽度通过振幅调整装置在整个区域中进行调整，然后由两个信号加法放大装置再次相加，使得输出信号SHS的振幅被调整到SHR -2，并且设置预定阈值以提取噪声。

公开(公告)号：US20110128274A1

公开(公告)日：2011-06-02

申请号：US13022995

申请日：2011-02-08

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru ITO ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru ITO ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： G06F3/038

CPC分类号： H01L27/0207 ,  G09G3/3688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116

摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

摘要翻译： 集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND，以及 与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端处的焊盘PD。 焊盘PD设置在第一和第二晶体管NTr1和PTr1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr1和PTr1中的至少一个晶体管的一部分或全部重叠。

公开(公告)号：US20100194307A1

公开(公告)日：2010-08-05

申请号：US12484265

申请日：2009-06-15

申请人： Takafumi Nonaka ,  Takashi Kumagai ,  Noriyuki Matsubara ,  Kazuo Ban ,  Koichi Saito

发明人： Takafumi Nonaka ,  Takashi Kumagai ,  Noriyuki Matsubara ,  Kazuo Ban ,  Koichi Saito

IPC分类号： H05B37/02 ,  H02J3/00

CPC分类号： H05B33/0815 ,  H02M1/32 ,  H02M3/33523 ,  H05B33/0824 ,  Y10T307/406

摘要： A series load circuit is a circuit formed by connecting a light-emitting device unit 851 (the first load circuit) and a light-emitting device unit 852 (the second load circuit) in series. A voltage generating circuit 111 generates voltage to be applied to the series load circuit. A current detecting circuit 112 detects electric current flowing through the light-emitting device unit 851. A controlling circuit 114 controls the voltage generating circuit 111 so that the electric current detected by the current detecting circuit 112 becomes a predetermined current value.

摘要翻译： 串联负载电路是通过串联连接发光器件单元851（第一负载电路）和发光器件单元852（第二负载电路）而形成的电路。 电压产生电路111产生施加到串联负载电路的电压。 电流检测电路112检测流过发光器件单元851的电流。控制电路114控制电压产生电路111，使得由电流检测电路112检测的电流变为预定电流值。

公开(公告)号：US20100177540A1

公开(公告)日：2010-07-15

申请号：US12715430

申请日：2010-03-02

申请人： Akihiko Iwata ,  Makoto Seto ,  Masaki Yamada ,  Shigeki Harada ,  Noriyuki Matsubara ,  Takashi Kumagai

发明人： Akihiko Iwata ,  Makoto Seto ,  Masaki Yamada ,  Shigeki Harada ,  Noriyuki Matsubara ,  Takashi Kumagai

IPC分类号： H02M7/48

CPC分类号： H02J3/383 ,  H02M7/483 ,  H02M2001/007 ,  H02M2001/0077 ,  Y02E10/563

摘要： In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting.

摘要翻译： 在提高太阳光电压的电力转换装置中，将其转换为交流电并向负载或系统提供AC电力，降低功率损耗并提高效率。 三相单相逆变器的AC侧以相互输入的电压比为1：3：9的各个电源的DC电源串联连接的逆变器单元。 使用各自产生的AC电压的和来执行输出电压的等级输出电压控制。 此外，太阳能光伏电压由斩波电路升压以产生最高电压的直流电源。 当太阳光电压超过预定电压时，斩波电路的升压停止，由此降低由于升压引起的功率损耗。

公开(公告)号：US07755587B2

公开(公告)日：2010-07-13

申请号：US11477715

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/2096 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2310/0289 ,  G09G2320/0285 ,  G09G2320/0673 ,  G09G2330/028 ,  G09G2330/04 ,  G09G2360/18

摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

摘要翻译： 集成电路装置包括：当从集成电路装置的短边的第一侧向与第一侧相反的第三侧的方向为方向D1时，沿着方向D1设置的第一至第N电路块CB1至CBN为方向D1， 从集成电路装置的长边的第二侧向与第二侧相反的第四侧的方向为方向D2。 电路块CB1至CBN的两端的至少一个电路块是用于驱动扫描线的扫描驱动器块。 或者，扫描驱动块SB沿方向D2的第一至第N电路块侧的方向D1设置。

公开(公告)号：US07719865B2

公开(公告)日：2010-05-18

申请号：US11816456

申请日：2006-02-21

申请人： Akihiko Iwata ,  Makoto Seto ,  Masaki Yamada ,  Shigeki Harada ,  Noriyuki Matsubara ,  Takashi Kumagai

发明人： Akihiko Iwata ,  Makoto Seto ,  Masaki Yamada ,  Shigeki Harada ,  Noriyuki Matsubara ,  Takashi Kumagai

IPC分类号： H02M7/49

CPC分类号： H02J3/383 ,  H02M7/483 ,  H02M2001/007 ,  H02M2001/0077 ,  Y02E10/563

摘要： In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting.

摘要翻译： 在提高太阳光电压的电力转换装置中，将其转换为交流电并向负载或系统提供AC电力，降低功率损耗并提高效率。 三相单相逆变器的AC侧以相互输入的电压比为1：3：9的各个电源的DC电源串联连接的逆变器单元。 使用各自产生的AC电压的和来执行输出电压的等级输出电压控制。 此外，太阳能光伏电压由斩波电路升压以产生最高电压的直流电源。 当太阳光电压超过预定电压时，斩波电路的升压停止，由此降低由于升压引起的功率损耗。

公开(公告)号：US07522592B2

公开(公告)日：2009-04-21

申请号：US10954475

申请日：2004-10-01

申请人： Tatsuo Kanetake ,  Kazuo Sugai ,  Takashi Kumagai

发明人： Tatsuo Kanetake ,  Kazuo Sugai ,  Takashi Kumagai

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L49/552 ,  H04L49/3009 ,  H04L49/354

摘要： The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.

公开(公告)号：US07471573B2

公开(公告)日：2008-12-30

申请号：US11270549

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G11C7/00

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/3611 ,  G09G5/39 ,  G09G5/395 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2360/12

摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

摘要翻译： 一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个 位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

公开(公告)号：US07411804B2

公开(公告)日：2008-08-12

申请号：US11270779

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB. The row address decoder RD is disposed so that a longitudinal direction of the row address decoder RD coincides with the direction D1, and the sense amplifier block SAB is disposed so that a longitudinal direction of the sense amplifier block SAB coincides with the direction D2.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D1是从集成电路装置的第一侧向与第三方向相反的第三侧的方向时 第一侧，第一侧为短边，当第二方向D 2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。 电路块CB 1至CBN包括存储图像数据的至少一个存储器块MB和驱动数据线的至少一个数据驱动器块DB; 并且存储块MB包括存储单元阵列，行地址解码器RD和读出放大器块SAB。 行地址解码器RD被布置成使得行地址解码器RD的纵向与方向D1一致，并且读出放大器块SAB被布置成使得读出放大器块SAB的纵向方向与方向D 2重合 。

公开(公告)号：US07388803B2

公开(公告)日：2008-06-17

申请号：US11270547

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G11C8/00 ,  G09G5/00

CPC分类号： G09G3/20 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2310/08

摘要： An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

摘要翻译： 集成电路装置包括：包括多个字线的RAM块，多个位线，多个存储单元和字线控制电路; 以及基于从RAM块提供的数据驱动显示面板的多个数据线组的数据线驱动器块。 数据线驱动器块包括第一至第N（N是大于1的整数）分割数据线驱动器块，驱动数据线组的不同数据线组的第一至第N分割数据线驱动器块中的每一个。 字线控制电路在显示面板的一个水平扫描周期中从字线中驱动相同的字线N次。 第一至第N分割数据线驱动器沿着位线延伸的第一方向布置。