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91.发明授权Semiconductor device, method of manufacturing semiconductor device and communication method 失效半导体器件，半导体器件的制造方法和通信方法公开(公告)号：US06703953B2
公开(公告)日：2004-03-09
申请号：US09457721
申请日：1999-12-10
IPC分类号： H03M166
CPC分类号： H01L23/57 , H01L2223/5444 , H01L2924/0002 , H04M1/67 , H04W12/12 , H01L2924/00
摘要： A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.
摘要翻译： 在多晶半导体层（1）上形成沟道区（2），源区（3）和漏区（4）。 多晶TFT（101）的特性通过包含在沟道区域（2）中的晶粒边界（6）的量而分散。 随着沟道区域（2）中包含的晶界（6）的量增加，漏电流减小。 为了利用通过对用于识别半导体芯片，系统等的TFT（101）的电特性进行编码而获得的代码，TFT（101）安装在半导体芯片，系统等上以及 一个编码器电路。 因此，以低成本提高了防止非法使用用户终端的屏障。
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92.发明授权Semiconductor device including a contact connected to the body and method of manufacturing the same 有权包括连接到身体的接触件的半导体器件及其制造方法公开(公告)号：US07402865B2
公开(公告)日：2008-07-22
申请号：US11210666
申请日：2005-08-25
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/84
摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。
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公开(公告)号：US20080128814A1
公开(公告)日：2008-06-05
申请号：US12003273
申请日：2007-12-21
IPC分类号： H01L27/088
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
摘要翻译： 在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即， （隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。
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公开(公告)号：US07358555B2
公开(公告)日：2008-04-15
申请号：US11409040
申请日：2006-04-24
IPC分类号： H01L27/108
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered.Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。
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公开(公告)号：US07352049B2
公开(公告)日：2008-04-01
申请号：US11500340
申请日：2006-08-08
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L29/00
CPC分类号： H01L27/0617 , H01L21/76283 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/13 , H01L28/10 , H01L28/20 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层3上，以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。
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公开(公告)号：US07307318B2
公开(公告)日：2007-12-11
申请号：US11137586
申请日：2005-05-26
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
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公开(公告)号：US20070158691A1
公开(公告)日：2007-07-12
申请号：US11619874
申请日：2007-01-04
申请人： Yukio Maki , Takashi Ipposhi , Toshiaki Iwamatsu
发明人： Yukio Maki , Takashi Ipposhi , Toshiaki Iwamatsu
IPC分类号： H01L27/10 , H01L21/4763
CPC分类号： H01L21/84 , H01L21/743 , H01L23/585 , H01L27/1203 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/13091 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.
摘要翻译： 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。
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公开(公告)号：US20060237726A1
公开(公告)日：2006-10-26
申请号：US11409040
申请日：2006-04-24
IPC分类号： H01L29/04
CPC分类号： H01L27/0811 , H01L27/1203
摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。
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公开(公告)号：US20060043494A1
公开(公告)日：2006-03-02
申请号：US11210666
申请日：2005-08-25
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/84
摘要： A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.
摘要翻译： 在SOI层和触点之间的连接处（即，在元件隔离绝缘膜下）形成肖特基结，而不形成具有高杂质浓度的P + +区域。 身体接触的表面提供阻挡金属。 作为阻挡金属和SOI层的反应的结果，在本体接触和SOI层之间形成硅化物。
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公开(公告)号：US20050269637A1
公开(公告)日：2005-12-08
申请号：US11137586
申请日：2005-05-26
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/105 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
摘要翻译： 在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即， （隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。
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