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194 条记录 (耗时 0.036 秒)

    Memory and driving method of the same
    91.
    发明申请
    Memory and driving method of the same 有权
    内存和驱动方法相同

    公开(公告)号：US20070076515A1

    公开(公告)日：2007-04-05

    申请号：US11607053

    申请日：2006-12-01

    申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

    摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

    摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

    Pulse Output Circuit, Shift Register and Electronic Equipment
    94.
    发明申请
    Pulse Output Circuit, Shift Register and Electronic Equipment 审中-公开
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US20060280279A1

    公开(公告)日：2006-12-14

    申请号：US11467022

    申请日：2006-08-24

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。 然后，随后阶段的输出被输入到TFT 103以使TFT 103导通，同时TFT 102和106的节点α的电位下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

    Circuit having source follower and semiconductor device having the circuit
    95.
    发明申请
    Circuit having source follower and semiconductor device having the circuit 有权

    公开(公告)号：US20060238221A1

    公开(公告)日：2006-10-26

    申请号：US11474938

    申请日：2006-06-27

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： H03K19/094

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    Memory and driving method of the same
    99.
    发明申请
    Memory and driving method of the same 有权
    内存和驱动方法相同

    公开(公告)号：US20050047266A1

    公开(公告)日：2005-03-03

    申请号：US10890173

    申请日：2004-07-14

    申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C11/4094 ,  G11C11/418 ,  G11C11/419 ,  G11C17/08 ,  G11C17/12 ,  H03K17/00 ,  H03K17/687 ,  H03K17/693

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

    摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

    摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

    Digital driver and display device
    100.
    发明申请
    Digital driver and display device 失效
    数字驱动器和显示设备

    公开(公告)号：US20050024242A1

    公开(公告)日：2005-02-03

    申请号：US10926956

    申请日：2004-08-27

    申请人： Jun Koyama ,  Yutaka Shionoiri

    发明人： Jun Koyama ,  Yutaka Shionoiri

    IPC分类号： G09G3/36 ,  G09G3/38 ,  H03M9/00

    CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0252 ,  G11C19/00 ,  G11C19/28 ,  H03M9/00

    摘要： A digital driver for display devices which can prevent the delay of digital data and the extended transition time of the digital data, and thus can make good display, and a display device including the above-mentioned digital driver are disclosed. The digital driver according to the present invention is constituted in such a manner that, by successively inputting digital data to a shift register, the digital data are shifted in the shift register, and the resulting output is sent out to latch circuits. Since the digital data are directly inputted to the shift register, the distance over which the data lines are laid around can be shortened, the increase in load due to the laying-around of the data lines which has so far been a problem can be prevented, and the delay of the digital data and the extended transition time of the digital data can be prevented.

    摘要翻译： 一种用于显示装置的数字驱动器，其可以防止数字数据的延迟和数字数据的延长的转换时间，并且因此可以进行良好的显示，并且公开了包括上述数字驱动器的显示装置。 根据本发明的数字驱动器以这样的方式构成，即通过将数字数据连续地输入到移位寄存器，数字数据在移位寄存器中移位，并将所得到的输出发送到锁存电路。 由于数字数据被直接输入到移位寄存器，所以可以缩短数据线的铺设距离，因此可以防止由于到目前为止存在问题的数据线的铺设而导致的负载增加。 ，并且可以防止数字数据的延迟和数字数据的扩展转换时间。