公开(公告)号：US08878330B2

公开(公告)日：2014-11-04

申请号：US13567456

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L29/02 ,  H01L21/761 ,  H01L21/266

CPC分类号： H01L21/761 ,  H01L21/266

摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

摘要翻译： 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US08592900B2

公开(公告)日：2013-11-26

申请号：US13288690

申请日：2011-11-03

申请人： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

发明人： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC分类号： H01L21/00

CPC分类号： H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

摘要翻译： 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

公开(公告)号：US08476127B2

公开(公告)日：2013-07-02

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US20120100679A1

公开(公告)日：2012-04-26

申请号：US13274698

申请日：2011-10-17

申请人： Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/8238

CPC分类号： H01L21/823456 ,  H01L21/823462

摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一个栅介质层，并保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。

公开(公告)号：US08148228B2

公开(公告)日：2012-04-03

申请号：US11696829

申请日：2007-04-05

申请人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

发明人： Sameer Pendharkar ,  Binghua Hu ,  Xinfen Celia Chen

IPC分类号： H01L21/8228

CPC分类号： H01L29/7322 ,  H01L23/544 ,  H01L29/41708 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

摘要翻译： 一种用于制造半导体器件的方法，包括在衬底的阱区中注入第一掺杂剂类型以形成由所述阱区的非植入区域分离的注入的子区。 该方法还包括在阱区上形成氧化物层，使得注入的子区域的氧化物转化的第一厚度大于非植入区域的氧化物转化的第二厚度。 该方法还包括去除氧化物层以在阱区上形成形貌特征。 地形特征包括较高和较低部分的表面图案。 更高的部分对应于非植入区域的位置，并且下部对应于植入的子区域。

公开(公告)号：US08124482B2

公开(公告)日：2012-02-28

申请号：US13006589

申请日：2011-01-14

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20110275210A1

公开(公告)日：2011-11-10

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：US07989853B2

公开(公告)日：2011-08-02

申请号：US12537589

申请日：2009-08-07

申请人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

发明人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

IPC分类号： H01L29/66 ,  H01L21/337

CPC分类号： H01L27/098 ,  H01L29/0649 ,  H01L29/1058 ,  H01L29/402 ,  H01L29/808

摘要： A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

摘要翻译： 公开了可以集成在IC中而不添加工艺步骤的双通道JFET。 夹断电压由源触点附近的第一垂直通道的横向宽度决定。 最大漏极电压由漏极到栅极间隔和栅极下方的第二个水平沟道的长度决定。 夹断电压和最大漏极电位取决于漏极和栅极阱的横向尺寸，并且可以独立优化。 还公开了制造双通道JFET的方法。

公开(公告)号：US07943472B2

公开(公告)日：2011-05-17

申请号：US12023190

申请日：2008-01-31

申请人： Sameer Pendharkar ,  Eugen Pompiliu Mindricelu

发明人： Sameer Pendharkar ,  Eugen Pompiliu Mindricelu

IPC分类号： H01L21/329 ,  H01L21/20

CPC分类号： H01L27/0814 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0619 ,  H01L29/47 ,  H01L29/872

摘要： Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation.

摘要翻译： 根据当前技术制造的硅化硅（CoSi 2）肖特基二极管在反向偏压下遭受过量的漏电流。 在本发明中，浮动p型区域包围由一个或多个CoSi 2阳极组成的CoSi 2肖特基二极管的每个阳极。 所得的p-n结在肖特基结下形成耗尽区，在反向偏压操作中减少穿过肖特基二极管的漏电流。

公开(公告)号：US20100314670A1

公开(公告)日：2010-12-16

申请号：US12789040

申请日：2010-05-27

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

IPC分类号： H01L29/78 ,  H01L29/04

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7846

摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。