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公开(公告)号：US07414472B2
公开(公告)日：2008-08-19
申请号：US11618071
申请日：2006-12-29
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译： 公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2） 第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管 与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度 。
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公开(公告)号：US20080100366A1
公开(公告)日：2008-05-01
申请号：US11812371
申请日：2007-06-18
IPC分类号： G06G7/14
CPC分类号： H03M1/0614 , H03M1/121
摘要： A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights ki (i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l1 (i=1 to 4), and adding the divided signals Vout1 to Vout4 weighted by the second weights. The first weights are k1=t, k2=−t, k3=1, k4=−1, while the second weights are l1=−1, l2=1, l3=t3, l4=−t3. Here, t=b/a (where a and b are different positive integers).
摘要翻译： 一种信号处理方法和装置，通过使用第一权重k i i（i = 1〜4）对输入信号进行加权，仅使幅度不同的分割信号减少失真，以获得分割信号，执行相同的信号处理f （x）对所分割的信号进行加权，通过第二权重I 1（i = 1至4）对信号处理的分频信号进行加权，并将分频信号V OUT1加到V 由第二权重加权的 out4 。 第一个权重是k 1 = t，k 2 = - t，k 3 = 1，k 4＆lt; 4＆gt; = -1，而第二权重为l 1 = -1，则1 = 1，1/3 3 = t 3， / SUP>，1＆lt; 4＆gt; = - 3＆lt; 3＆gt; 3。 这里，t = b / a（其中 a和 b是不同的正整数）。
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公开(公告)号：US20060187100A1
公开(公告)日：2006-08-24
申请号：US11409603
申请日：2006-04-24
申请人： Daisuke Kurose , Takafumi Yamaji , Tetsuro Itakura
发明人： Daisuke Kurose , Takafumi Yamaji , Tetsuro Itakura
IPC分类号： H03M3/00
CPC分类号： H03M1/123 , H03M1/0695 , H03M1/1205 , H03M1/44
摘要： A multiple input AD conversion apparatus includes a first unit AD converter including a plurality of first conversion stages connected in cascade to convert a first analog input signal to a first digital output signal, a second unit AD converter including a plurality of second conversion stages connected in cascade to convert a second analog input signal to a second digital output signal, and an operational amplifier shared between the first conversion stage and the second conversion stage in a time sharing.
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公开(公告)号：US07053703B2
公开(公告)日：2006-05-30
申请号：US10811908
申请日：2004-03-30
申请人： Tetsuro Itakura , Takafumi Yamaji
发明人： Tetsuro Itakura , Takafumi Yamaji
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , G11C27/024 , G11C27/026 , H03F3/45632 , H03F3/45928 , H03F3/45977 , H03F2203/45101 , H03F2203/45138 , H03F2203/45428 , H03F2203/45574 , H03H11/1243 , H03H11/32
摘要： An operational amplifier circuit is constituted by first and second inverted amplifier circuits (A1, A2) that receive first and second input signals, a third inverted amplifier circuit (A3) that receives an estimated common-mode output signal and an output signal from the first inverted amplifier circuit and outputs first and second output signals, a fourth inverted amplifier circuit (A4) that receives the estimated common-mode output signal and an output signal from the second inverted amplifier circuit and outputs third and fourth output signals, where the estimated common-mode output signal is generated by adding the second output signal and the fourth output signal, and first and second non-inverted amplifier circuits (A5, A6) that receive the estimated common-mode output signal and feed it back to the first and second inverted amplifier circuits.
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公开(公告)号：US07038537B2
公开(公告)日：2006-05-02
申请号：US11216097
申请日：2005-09-01
申请人： Tetsuro Itakura , Takafumi Yamaji
发明人： Tetsuro Itakura , Takafumi Yamaji
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , G11C27/024 , G11C27/026 , H03F3/45632 , H03F3/45928 , H03F3/45977 , H03F2203/45101 , H03F2203/45138 , H03F2203/45428 , H03F2203/45574 , H03H11/1243 , H03H11/32
摘要： An operational amplifier circuit is constituted by first and second inverted amplifier circuits (A1, A2) that receive first and second input signals, a third inverted amplifier circuit (A3) that receives an estimated common-mode output signal and an output signal from the first inverted amplifier circuit and outputs first and second output signals, a fourth inverted amplifier circuit (A4) that receives the estimated common-mode output signal and an output signal from the second inverted amplifier circuit and outputs third and fourth output signals, where the estimated common-mode output signal is generated by adding the second output signal and the fourth output signal, and first and second non-inverted amplifier circuits (A5, A6) that receive the estimated common-mode output signal and feed it back to the first and second inverted amplifier circuits.
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96.发明授权Operational amplifier circuit, sample/hold circuit and filter circuit using the operational amplifier circuit 失效运算放大器电路，采样/保持电路和使用运算放大器电路的滤波电路公开(公告)号：US07009448B2
公开(公告)日：2006-03-07
申请号：US11216100
申请日：2005-09-01
申请人： Tetsuro Itakura , Takafumi Yamaji
发明人： Tetsuro Itakura , Takafumi Yamaji
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , G11C27/024 , G11C27/026 , H03F3/45632 , H03F3/45928 , H03F3/45977 , H03F2203/45101 , H03F2203/45138 , H03F2203/45428 , H03F2203/45574 , H03H11/1243 , H03H11/32
摘要： An operational amplifier circuit is constituted by first and second inverted amplifier circuits (A1, A2) that receive first and second input signals, a third inverted amplifier circuit (A3) that receives an estimated common-mode output signal and an output signal from the first inverted amplifier circuit and outputs first and second output signals, a fourth inverted amplifier circuit (A4) that receives the estimated common-mode output signal and an output signal from the second inverted amplifier circuit and outputs third and fourth output signals, where the estimated common-mode output signal is generated by adding the second output signal and the fourth output signal, and first and second non-inverted amplifier circuits (A5, A6) that receive the estimated common-mode output signal and feed it back to the first and second inverted amplifier circuits.
摘要翻译： 运算放大器电路由接收第一和第二输入信号的第一和第二反相放大器电路（A 1，A 2）构成，第三反相放大器电路（A 3），其接收估计的共模输出信号和输出信号 从第一反相放大器电路输出第一和第二输出信号;第四反相放大电路（A 4），其接收估计的共模输出信号和来自第二反相放大器电路的输出信号，并输出第三和第四输出信号; 其中通过将第二输出信号和第四输出信号相加来产生估计的共模输出信号，以及接收估计的共模输出信号并将其馈送的第一和第二非反相放大器电路（A 5，A 6） 回到第一和第二反相放大器电路。
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公开(公告)号：US06954089B2
公开(公告)日：2005-10-11
申请号：US10776199
申请日：2004-02-12
申请人： Toshiyuki Umeda , Shoji Otaka , Tetsuro Itakura
发明人： Toshiyuki Umeda , Shoji Otaka , Tetsuro Itakura
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0084
摘要： A frequency converter configured to convert a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency is disclosed, which comprises an adder configured to add the first current signal and a predetermined reference current signal to output a third current signal corresponding to the sum of the first current signal and the reference current signal, and a switching circuit configured to pass only that portion of the third current signal which is larger in magnitude than a threshold current to output the second current signal.
摘要翻译： 公开了一种频率转换器，其被配置为将具有第一频率的第一电流信号转换成具有与第一频率不同的第二频率的第二电流信号，其包括加法器，其被配置为将第一电流信号和预定参考电流信号相加以输出 第三电流信号对应于第一电流信号和参考电流信号的和，以及开关电路，其被配置为仅通过大于阈值电流的第三电流信号的大小部分以输出第二电流信号。
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公开(公告)号：US06549196B1
公开(公告)日：2003-04-15
申请号：US09401847
申请日：1999-09-22
申请人： Takashi Taguchi , Takeshi Shima , Tetsuro Itakura
发明人： Takashi Taguchi , Takeshi Shima , Tetsuro Itakura
IPC分类号： B09G500
CPC分类号： H03M1/0872 , G09G3/3688 , G09G2310/027 , H03M1/765
摘要： A D/A conversion circuit which can perform D/A conversion at high speed and with high precision is disclosed. The D/A conversion circuit comprises an analog reference power supply, an output buffer, a multiplexer, a pre-buffer, and a current changeover switch. The pre-buffer operates with a power supply voltage different from that of the analog reference power supply, and outputs a voltage substantially equal to an output voltage of the analog reference power supply. For a predetermined period after logic of digital data changes, the output voltage of the pre-buffer is supplied to the output buffer, and an input parasitic capacitor of the output buffer is charged/discharged. After the predetermined period elapses, the output voltage of the analog reference power supply is supplied to the output buffer. Therefore, a charging/discharging current of the input parasitic capacitor does not flow through the analog reference power supply, and fluctuation of the output voltage of the analog reference power supply can be suppressed.
摘要翻译： 公开了一种可以高速，高精度地执行D / A转换的D / A转换电路。 D / A转换电路包括模拟参考电源，输出缓冲器，多路复用器，预缓冲器和电流切换开关。 预缓冲器以与模拟基准电源不同的电源电压工作，并输出基本上等于模拟基准电源的输出电压的电压。 在数字数据的逻辑变化之后的预定时间内，预缓冲器的输出电压被提供给输出缓冲器，并且输出缓冲器的输入寄生电容器被充电/放电。 经过预定时间后，模拟基准电源的输出电压被提供给输出缓冲器。 因此，输入的寄生电容器的充电/放电电流不会流过模拟基准电源，并且可以抑制模拟基准电源的输出电压的波动。
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99.发明授权Receiver having DC offset decreasing function and communication system using the same 失效具有DC偏移减小功能的接收机和使用该功能的通信系统公开(公告)号：US06498929B1
公开(公告)日：2002-12-24
申请号：US08880679
申请日：1997-06-23
申请人： Hiroshi Tsurumi , Hiroshi Yoshida , Tetsuro Itakura , Takafumi Yamaji , Akira Yasuda , Takashi Ueno , Hiroshi Tanimoto , Ryuichi Fujimoto , Hiroshi Horiguchi
发明人： Hiroshi Tsurumi , Hiroshi Yoshida , Tetsuro Itakura , Takafumi Yamaji , Akira Yasuda , Takashi Ueno , Hiroshi Tanimoto , Ryuichi Fujimoto , Hiroshi Horiguchi
IPC分类号： H04B716
CPC分类号： H03D3/008 , H03G3/3052 , H04B1/30
摘要： A receiver having a function of a direct current offset, and including a receiving section for receiving a radio frequency signal, an analog signal processing section for amplifying, band-converting and frequency-converting an analog signal inputted from the receiving section, and an AD converting section for converting an output of the analog signal processing section from an analog signal to a digital signal. Also included is a digital signal processing section for processing the digital signal converted by the DC converting section. The receiver further includes an offset detecting element, provided in the digital signal processing section, for detecting a direct current offset signal produced in the receiving section or a frequency converting section, an offset holding element, provided in the digital signal processing section, for holding the direct current offset signal detected by the offset detecting element, a DA converting section for converting the direct current offset signal detected by the digital signal processing section into an analog signal, and a first offset correcting element, provided in the analog signal processing section, for correcting the analog signal on the basis of the direct current offset signal converted by the DA converting section into the analog signal.
摘要翻译： 具有直流偏移功能的接收机，包括用于接收射频信号的接收部分，用于放大从接收部分输入的模拟信号的频带转换和频率转换的模拟信号处理部分，以及AD 转换部分，用于将模拟信号处理部分的输出从模拟信号转换成数字信号。 还包括用于处理由DC转换部分转换的数字信号的数字信号处理部分。 接收机还包括偏移检测元件，设置在数字信号处理部分中，用于检测在数字信号处理部分中设置的接收部分或频率转换部分产生的直流偏移信号，偏移保持元件，用于保持 由偏移检测元件检测的直流偏移信号，用于将由数字信号处理部分检测的直流偏移信号转换为模拟信号的DA转换部分和设置在模拟信号处理部分中的第一偏移校正元件， 用于基于由DA转换部分转换成的模拟信号的直流偏移信号来校正模拟信号。
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公开(公告)号：US5995819A
公开(公告)日：1999-11-30
申请号：US755468
申请日：1996-11-22
申请人： Takafumi Yamaji , Osamu Watanabe , Hiroshi Tanimoto , Tetsuro Itakura , Shoji Otaka , Ryuichi Fujimoto
发明人： Takafumi Yamaji , Osamu Watanabe , Hiroshi Tanimoto , Tetsuro Itakura , Shoji Otaka , Ryuichi Fujimoto
CPC分类号： H03F3/45085 , H03D7/00 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D2200/0007 , H03D2200/0025 , H03D2200/0047 , H03D2200/009
摘要： A frequency converter includes: a signal synthesizer element for inputting first and second input signals to synthesize these signals and for outputting a synthesized signal, from which noises even times as large as the frequency of the second input signal are removed; an amplitude limitation amplifier element, composed of a differential amplifier circuit, for amplifying the synthesized signal outputted from the signal synthesizer element to output an amplified signal having a constant amplitude; and a filter for inputting the amplified signal outputted from the amplitude limitation amplifier element, to remove an unnecessary signal component to produce an output a baseband signal including only a desired signal component. In addition, a radio receiver using the frequency converter of such a construction is designed to input the output of a local oscillator to a variable attenuator or a variable gain amplifier, to input the output of the variable attenuator or the variable gain amplifier as the first input signal to the frequency converter so as to perform the gain control. Thus, not only is self-mixing, a common problem in direct conversion receivers, prevented, but also, because a smaller local oscillation driving signal is required, power consumption is significantly reduced.
摘要翻译： 一种频率转换器，包括：信号合成器元件，用于输入第一和第二输入信号以合成这些信号并输出合成信号，从该信号合成信号除去除了第二输入信号的频率以上的噪声; 幅度限制放大器元件，由差分放大电路组成，用于放大从信号合成器元件输出的合成信号，以输出具有恒定幅度的放大信号; 以及滤波器，用于输入从幅度限制放大器元件输出的放大信号，以去除不必要的信号分量以产生仅包括所需信号分量的基带信号。 此外，使用这种结构的变频器的无线电接收机被设计成将本地振荡器的输出输入到可变衰减器或可变增益放大器，以将可变衰减器或可变增益放大器的输出作为第一 输入到变频器的信号，以进行增益控制。 因此，不仅自发混合，直接转换接收器中的常见问题被阻止，而且由于需要较小的本地振荡驱动信号，所以功耗显着降低。
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