公开(公告)号：US20110234331A1

公开(公告)日：2011-09-29

申请号：US12748261

申请日：2010-03-26

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC: H03B5/12 ,  H01F5/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract translation: 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US07996749B2

公开(公告)日：2011-08-09

申请号：US11773234

申请日：2007-07-03

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03M13/03

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US20110188564A1

公开(公告)日：2011-08-04

申请号：US13079420

申请日：2011-04-04

Applicant: Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

Inventor： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC: H03K5/125 ,  H03K5/19

CPC classification number: H04L25/03885

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract translation: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07986160B2

公开(公告)日：2011-07-26

申请号：US11420737

申请日：2006-05-27

Applicant: Tim Tri Hoang ,  Sergey Shumarayev

Inventor： Tim Tri Hoang ,  Sergey Shumarayev

IPC: H03K17/16 ,  H03K19/173

CPC classification number: H03K19/0016 ,  G06F17/5054 ,  G06F2217/84 ,  H01L2924/0002 ,  H03K19/00369 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17784 ,  H03K19/17792 ,  H01L2924/00

Abstract: A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.

Abstract translation: PLD包括至少一个IP块或电路，以及至少一个I / O块或电路。 调整至少一个IP块的性能，以便通过改变至少一个IP块的供应水平，通过调整IP块的至少一个体偏置水平，或两者来满足至少一个性能特征。 通过调整I / O块的至少一个体偏置电平或两者来改变至少一个I / O块的电源电平来调整至少一个I / O块的性能。

公开(公告)号：US07750674B2

公开(公告)日：2010-07-06

申请号：US12214466

申请日：2008-06-18

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Richard G. Cliff

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17784

Abstract: High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.

Abstract translation: 可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。 该范围包括高性能应用和PLD降低功耗很重要的应用。 在后一种情况下，可以使用任何一种或多种各种特征来帮助降低功耗。

公开(公告)号：US20100058099A1

公开(公告)日：2010-03-04

申请号：US12576507

申请日：2009-10-09

Applicant: Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC: G06F1/04 ,  G06F1/12

CPC classification number: H04L5/14 ,  H03K19/17744 ,  H04L27/00

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract translation: 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US20090284292A1

公开(公告)日：2009-11-19

申请号：US12511024

申请日：2009-07-28

Applicant: Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

Inventor： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

IPC: H03K5/12

CPC classification number: H04B7/005 ,  H04L25/03006 ,  H04L25/061

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

公开(公告)号：US20090257445A1

公开(公告)日：2009-10-15

申请号：US12100360

申请日：2008-04-09

Applicant: Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

Inventor： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC: H04L12/66

CPC classification number: H04L49/30 ,  H04L49/352

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US07586983B1

公开(公告)日：2009-09-08

申请号：US11510446

申请日：2006-08-24

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K5/159 ,  H04B1/10

CPC classification number: H04L25/03057

Abstract: In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

Abstract translation: 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

公开(公告)号：US07541857B1

公开(公告)日：2009-06-02

申请号：US11323571

申请日：2005-12-29

Applicant: Wilson Wong ,  Tin H. Lai ,  Sergey Shumarayev ,  Rakesh H. Patel

Inventor： Wilson Wong ,  Tin H. Lai ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC: H03L5/00

CPC classification number: H03F3/45183 ,  H03F3/45632 ,  H03F2203/45212 ,  H03F2203/45646 ,  H03F2203/45681 ,  H03F2203/45702 ,  H03F2203/45726

Abstract: An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

Abstract translation: 用于可编程器件的输入的阻抗补偿电路包括与输入节点连接的可编程阻抗电路。 可编程阻抗电路可以配置为向输入节点施加补偿电压以减少或消除不期望的失调电压。 阻抗补偿电路可以包括并联的串联或电流源的电阻器。 一组旁路开关选择性地将每个电阻器或电流源施加到输入节点，从而改变节点的偏移电压并补偿阻抗失配。 控制逻辑提供信号来控制旁路开关。 可以使用可编程设备资源实现控制逻辑，使得在设备的制造完成之后能够更新和改进控制逻辑。 控制逻辑可以随时自动评估偏移电压，并相应地改变补偿阻抗。 这降低了制造成本并考虑了温度和老化的影响。