公开(公告)号：US08450806B2

公开(公告)日：2013-05-28

申请号：US10814482

申请日：2004-03-31

申请人： Toshiharu Furukawa ,  Charles William Koburger, III ,  James Albert Slinkman

发明人： Toshiharu Furukawa ,  Charles William Koburger, III ,  James Albert Slinkman

IPC分类号： H01L27/12

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US07704855B2

公开(公告)日：2010-04-27

申请号：US11926613

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Charles William Koburger, III ,  James Albert Slinkman

发明人： Toshiharu Furukawa ,  Charles William Koburger, III ,  James Albert Slinkman

IPC分类号： H01L21/76 ,  H01L21/425

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US07129138B1

公开(公告)日：2006-10-31

申请号：US11106004

申请日：2005-04-14

申请人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

发明人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

IPC分类号： H01L21/762

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

摘要翻译： 提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。 将氧注入步骤从背面进行到薄化的硅衬底层。 退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。 氧注入步骤在氧植入物附近形成隔离区域。 背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

公开(公告)号：US07250351B2

公开(公告)日：2007-07-31

申请号：US11106002

申请日：2005-04-14

申请人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

发明人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

IPC分类号： H01L29/76

CPC分类号： H01L29/78687 ,  H01L21/26533 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78603

摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

摘要翻译： 提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。 增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。 在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

公开(公告)号：US08039334B2

公开(公告)日：2011-10-18

申请号：US12902944

申请日：2010-10-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US08004024B2

公开(公告)日：2011-08-23

申请号：US12348404

申请日：2009-01-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

摘要翻译： 晶体管。 晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

公开(公告)号：US20110034000A1

公开(公告)日：2011-02-10

申请号：US12907186

申请日：2010-10-19

申请人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Wesley C. Natzle

发明人： Ashima B. Chakravarti ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Wesley C. Natzle

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

摘要翻译： 在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗 氮化物表面而不是氧化物表面。

公开(公告)号：US07646469B2

公开(公告)日：2010-01-12

申请号：US11899085

申请日：2007-09-04

申请人： Steven J. Holmes ,  Toshiharu Furukawa ,  Charles W. Koburger, III ,  Naim Moumen

发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Charles W. Koburger, III ,  Naim Moumen

IPC分类号： G03B27/42 ,  G03B27/52

CPC分类号： G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

摘要翻译： 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

公开(公告)号：US20090321833A1

公开(公告)日：2009-12-31

申请号：US12145616

申请日：2008-06-25

申请人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

摘要翻译： 公开了通过在薄栅极电介质上电镀制造垂直轮廓FinFET栅电极的方法。 在一个实施例中，一种用于形成晶体管的方法包括：提供包括半导体衬底和在衬底上方延伸的半导体鳍片结构的半导体形貌; 在半导体拓扑的暴露表面上形成栅极电介质; 在半导体形貌上图案化掩模，使得仅限定限定要形成栅电极的位置的栅极电介质的选择部分; 以及在所述栅极电介质的所述选择部分上镀覆金属材料以在所述鳍结构的一部分上形成栅电极。

公开(公告)号：US07557023B2

公开(公告)日：2009-07-07

申请号：US11532189

申请日：2006-09-15

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/425

CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

摘要翻译： 半导体制造方法。 该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。 栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。 半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。 接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。 接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。