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    Selective post-doping of gate structures by means of selective oxide growth
    5.
    发明授权
    Selective post-doping of gate structures by means of selective oxide growth 失效
    通过选择性氧化物生长选择性地掺杂栅极结构

    公开(公告)号：US07288814B2

    公开(公告)日：2007-10-30

    申请号：US11268100

    申请日：2005-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/266 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

    摘要翻译： 提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。 本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。 可以使用常规图案化在单个基板上处理多个栅极区域。 在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

    Microelectronic structure by selective deposition
    9.
    发明授权
    Microelectronic structure by selective deposition 有权
    微电子结构通过选择性沉积

    公开(公告)号：US08138100B2

    公开(公告)日：2012-03-20

    申请号：US12273908

    申请日：2008-11-19

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

    摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

    摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁 鳍。 可以使用侧向生长方法制造其它微电子结构。