公开(公告)号：US20160131969A1

公开(公告)日：2016-05-12

申请号：US14996232

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G03F1/38

CPC classification number: G03F1/38 ,  G03F1/70 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845

Abstract: A mask set includes a first mask, a second mask, and a third mask respectively include a first layout pattern, a second layout pattern, and a third layout pattern. The first layout pattern includes mandrel patterns and dummy mandrel patterns. The second layout pattern includes geometric patterns covering portions of the mandrel patterns and portions of the dummy mandrel patterns. The third layout pattern includes dummy pad patterns which are laterally spaced apart from the mandrel patterns and the dummy mandrel patterns.

Abstract translation: 包括第一掩模，第二掩模和第三掩模的掩模组分别包括第一布局图案，第二布局图案和第三布局图案。 第一布局图案包括心轴图案和虚拟心轴图案。 第二布局图案包括覆盖心轴图案的部分和虚拟心轴图案的部分的几何图案。 第三布局图案包括与心轴图案和虚拟心轴图案横向隔开的虚拟垫图形。

公开(公告)号：US09330968B1

公开(公告)日：2016-05-03

申请号：US14534180

申请日：2014-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  G03F7/70466 ,  G03F7/70633 ,  G03F9/7046

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.

Abstract translation: 一种制造集成电路的方法包括以下步骤。 第一掩模版用于形成第一图案，第一对准标记和第二标线用于在同一层中形成第二图案和第二对准标记。 第三掩模版与第一对准标记和第二对准标记对准，以获得覆盖校正值; 此外，第三掩模版与第一对准标记对准以获得第一覆盖校正值，第三掩模版与第二对准标记对准以获得第二覆盖校正值，并且总重叠校正值通过将第 第一重叠校正值和第二覆盖校正值。 第三掩模版用于通过将第三掩模版与总覆盖校正值对准来形成第三图案。

公开(公告)号：US20150044831A1

公开(公告)日：2015-02-12

申请号：US13962959

申请日：2013-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  Chin-I Liao

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814

Abstract: A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成第一栅极和第二栅极。 形成第一应力层以覆盖第一栅极和第二栅极。 蚀刻覆盖第一栅极的第一应力层以在第一栅极旁边形成第一间隔物，但保留覆盖第二栅极的第一应力层。 在第一间隔物旁边形成第一外延层。 第一应力层和第一间隔件被完全去除。 形成第二应力层以覆盖第一栅极和第二栅极。 蚀刻覆盖第二栅极的第二应力层以在第二栅极旁边形成第二间隔物，但保留覆盖第一栅极的第二应力层。 在第二间隔物旁边形成第二外延层。 完全除去第二应力层和第二间隔物。

公开(公告)号：US20140201691A1

公开(公告)日：2014-07-17

申请号：US14215635

申请日：2014-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5045 ,  G06F17/5072

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

公开(公告)号：US20140077229A1

公开(公告)日：2014-03-20

申请号：US14089771

申请日：2013-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

公开(公告)号：US11069689B2

公开(公告)日：2021-07-20

申请号：US16789435

申请日：2020-02-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A contact hole is formed on a memory cell region of a semiconductor substrate and exposes a part of the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on a memory cell region of the semiconductor substrate. A second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. A contact structure is formed in the contact hole, and the contact structure is located between the bit line metal structure and the semiconductor substrate.

公开(公告)号：US10663853B2

公开(公告)日：2020-05-26

申请号：US15481479

申请日：2017-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/22 ,  G03F1/24

Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.

公开(公告)号：US10600790B2

公开(公告)日：2020-03-24

申请号：US15987919

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.

公开(公告)号：US20200083020A1

公开(公告)日：2020-03-12

申请号：US16143419

申请日：2018-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01J37/302 ,  H01J37/317

Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

公开(公告)号：US20200075397A1

公开(公告)日：2020-03-05

申请号：US16134982

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Hsuan-Tung Chu ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Yu-Cheng Tung ,  Chia-Lung Chang

IPC: H01L21/762 ,  H01L21/02

Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.