公开(公告)号：US20110254080A1

公开(公告)日：2011-10-20

申请号：US12760287

申请日：2010-04-14

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

公开(公告)号：US20110227165A1

公开(公告)日：2011-09-22

申请号：US13151525

申请日：2011-06-02

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L27/092

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

公开(公告)号：US08022488B2

公开(公告)日：2011-09-20

申请号：US12566004

申请日：2009-09-24

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

摘要翻译： 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。 该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。 第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。 扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

公开(公告)号：US07993999B2

公开(公告)日：2011-08-09

申请号：US12614906

申请日：2009-11-09

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

公开(公告)号：US09105577B2

公开(公告)日：2015-08-11

申请号：US13398151

申请日：2012-02-16

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

摘要翻译： SOI衬底，半导体器件和背栅功函数调谐方法。 衬底和器件具有多个金属背栅区域，其中至少两个区域具有不同的功函数。 该方法包括在衬底上形成掩模并且注入置于衬底氧化物和衬底的体区之间的金属背栅，从而产生具有不同剂量的杂质和不同功函数的至少两个金属背栅区。 工作功能区域可以对准，使得每个晶体管具有不同的阈值电压。 当顶栅电极用作掩模时，形成在沟道区下具有第一功函数的金属背栅和源/漏区下的第二功函数。 植入物可以倾斜以相对于掩模移动功函数区域。

公开(公告)号：US08916443B2

公开(公告)日：2014-12-23

申请号：US13534407

申请日：2012-06-27

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  H01L27/12 ,  G06F17/50

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

公开(公告)号：US08895379B2

公开(公告)日：2014-11-25

申请号：US13344806

申请日：2012-01-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Christian Lavoie

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Christian Lavoie

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/485 ,  H01L27/0883 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

摘要翻译： 结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。 栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。 该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。 第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。 每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。 还公开了制造该结构的方法。

公开(公告)号：US08860138B2

公开(公告)日：2014-10-14

申请号：US13531053

申请日：2012-06-22

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

公开(公告)号：US08853038B2

公开(公告)日：2014-10-07

申请号：US13614572

申请日：2012-09-13

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762

CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.

摘要翻译： 栅极堆叠形成在掩埋氧化物层上方的硅层上。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 在硅层和栅叠层上形成第一氮化物层。 在第一氮化物层上形成氧化物层。 在氧化物层上形成第二氮化物层。 蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。 蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。 与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。 使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。

公开(公告)号：US08835900B2

公开(公告)日：2014-09-16

申请号：US13154677

申请日：2011-06-07

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7841 ,  H01L21/8252 ,  H01L21/8254 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/10802 ,  H01L27/1203

摘要： A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.

摘要翻译： 一种用于制造浮体存储单元的浮体存储单元，存储器电路和方法。 浮体存储单元包括具有耦合到第二半导体的第一半导体的双层异质结。 第一半导体和第二半导体具有不同的能带隙。 浮体存储单元包括掩埋绝缘体层。 浮体存储单元包括通过至少掩埋绝缘层与双层异质结的第二半导体分离的背晶体管栅极。 浮体存储单元还包括耦合到双层异质结的第一半导体的前晶体管栅极。