公开(公告)号：US07859291B2

公开(公告)日：2010-12-28

申请号：US12325168

申请日：2008-11-29

申请人： Yeo-Hwang Kim

发明人： Yeo-Hwang Kim

IPC分类号： G01R31/26 ,  H01L27/088

CPC分类号： G01R31/2621 ,  H01L22/14

摘要： A method of measuring on-resistance in a backside drain wafer includes providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer, and then forming a current flow path passing through the first and second MOS transistors, and then measuring a resistance between the sources of the first and second MOS transistors. Accordingly, an on-resistance in a backside drain wafer can be measured without using a chuck.

摘要翻译： 一种在背面漏极晶片中测量导通电阻的方法包括提供具有第一MOS晶体管和第二MOS晶体管的晶片，每个晶体管具有源极，并且还共享设置在晶片背面的漏极，然后形成电流流路 通过第一和第二MOS晶体管，然后测量第一和第二MOS晶体管的源极之间的电阻。 因此，可以在不使用卡盘的情况下测量背面漏极晶片中的导通电阻。

公开(公告)号：US07851341B2

公开(公告)日：2010-12-14

申请号：US11844016

申请日：2007-08-23

申请人： Dong Ki Jeon

发明人： Dong Ki Jeon

IPC分类号： H01L21/00

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28556 ,  H01L29/78

摘要： A semiconductor device is provided including a transistor element on a substrate, a silicide on a gate and a source/drain of the transistor element; and an amorphous capping layer on the silicide.

摘要翻译： 提供一种半导体器件，其包括在衬底上的晶体管元件，栅极上的硅化物和晶体管元件的源极/漏极; 和硅化物上的非晶覆盖层。

公开(公告)号：US07851329B2

公开(公告)日：2010-12-14

申请号：US11955235

申请日：2007-12-12

申请人： Hyun-Soo Shin

发明人： Hyun-Soo Shin

IPC分类号： H01L21/76

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66659

摘要： A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.

摘要翻译： 提供具有EDMOS晶体管的半导体器件及其形成方法。 半导体器件包括在半导体衬底中分开形成的源极和漏极区域，填充在源极和漏极区域之间形成在衬底中的沟槽的第一栅极绝缘层，第一栅极绝缘层邻近漏极区域并与源极分离 形成在所述第一栅极绝缘层和所述源极区域之间的所述基板上的第二栅极绝缘层，所述第二栅极绝缘层比所述第一栅极绝缘层薄，形成在所述第一和第二栅极绝缘层上的栅电极，以及 掺杂漂移区，形成在所述第一栅极绝缘层下的所述衬底中，所述掺杂漂移区与所述漏极区接触。 这降低了EDMOS晶体管的平面面积，从而实现了高度集成的半导体器件。

公开(公告)号：US07851235B2

公开(公告)日：2010-12-14

申请号：US12172218

申请日：2008-07-12

申请人： Ji-Ho Hong

发明人： Ji-Ho Hong

IPC分类号： G01R31/26

CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule. Accordingly, the test element group can monitor leakage current caused by PN junction diodes formed by junction of the impurity regions and the well in the active areas in a semiconductor device or misalignment of contacts, and can accurately monitor micro-leakage current in a semiconductor device during manufacturing.

摘要翻译： 公开了一种用于监测半导体器件中的漏电流的测试元件组及其制造方法。 用于监测半导体器件中的漏电流的测试元件组包括在第一导电型半导体衬底上形成的器件隔离层。 可以在第一导电类型半导体衬底上形成第二导电类型阱。 可以在第二导电类型阱中的器件隔离层之间的第一有源区中形成第一导电类型的杂质区。 可以在第一有效区域内形成监测触点以监测泄漏电流，使用布局数据，使得从每个监测触点到每个第一有效区域的边界的距离被设定为在预定设计下具有允许的最小值 规则。 因此，测试元件组可以监视由半导体器件中的有源区域中的杂质区域和阱的结合形成的PN结二极管所引起的漏电流或触点的未对准，并且可以精确地监测半导体器件中的微漏电流 在制造过程中。

公开(公告)号：US07849436B2

公开(公告)日：2010-12-07

申请号：US11889384

申请日：2007-08-13

申请人： Choi Jae Young

发明人： Choi Jae Young

IPC分类号： G06F17/50

CPC分类号： H01L21/31053

摘要： A method of forming a dummy pattern on a mask for fabricating a semiconductor device is disclosed. The method may include a step of calculating a distance in a device isolation area between a first chip area and a second chip area having different pattern densities. In addition, the method may include comparing the distance and a first reference distance. The method may further include forming the dummy pattern in the device isolation area based on the comparison result. The dummy pattern may have a plurality of partitions. Each of the plurality of partitions may have a pattern density according to a position of the partition. A quantity of the partitions may be based on the comparison result. And at least one partition may have a pattern density which is substantially equal to an average of the pattern densities of the first and the second chip areas.

摘要翻译： 公开了一种在用于制造半导体器件的掩模上形成虚设图案的方法。 该方法可以包括计算具有不同图案密度的第一芯片区域和第二芯片区域之间的器件隔离区域中的距离的步骤。 此外，该方法可以包括比较距离和第一参考距离。 该方法还可以包括基于比较结果在设备隔离区域中形成虚设图案。 虚拟图案可以具有多个分区。 多个分区中的每一个可以具有根据分区的位置的图案密度。 一定数量的分区可以基于比较结果。 并且至少一个分区可以具有基本上等于第一和第二芯片区域的图案密度的平均值的图案密度。

公开(公告)号：US07843712B2

公开(公告)日：2010-11-30

申请号：US11849716

申请日：2007-09-04

申请人： Yong-Seop Lee

发明人： Yong-Seop Lee

IPC分类号： H02M3/18

CPC分类号： H02M3/07 ,  H02M2001/009 ,  H02M2003/071

摘要： A miniaturized system on a chip that incorporates a positive high voltage charge pump and a negative high voltage charge pump into one pump circuit and shares components. A voltage control apparatus in a semiconductor device may include at least one of the following: First and second input/output units capable of inputting or outputting voltage. A voltage booster that receives and boosts a voltage from one of the first and second input/output unit and outputs the boosted voltage from the other input/output unit. An output selector that receives the boosted voltage from the voltage booster and selects one of the positive or the negative voltage to output. An output controller that receives the boosted voltage from the voltage booster and controls and/or regulates the output voltage. An output unit that outputs the generated output voltage.

摘要翻译： 一个芯片上的小型化系统，将正高压电荷泵和负高压电荷泵并入一个泵电路并共享组件。 半导体器件中的电压控制装置可以包括以下中的至少一个：能够输入或输出电压的第一和第二输入/输出单元。 一种升压器，其接收并升压来自第一和第二输入/输出单元之一的电压，并从另一输入/输出单元输出升压电压。 输出选择器，其从升压器接收升压电压并选择正电压或负电压中的一个以输出。 输出控制器，其从升压器接收升压电压并控制和/或调节输出电压。 输出单元，输出产生的输出电压。

公开(公告)号：US07843065B2

公开(公告)日：2010-11-30

申请号：US12235889

申请日：2008-09-23

申请人： Cheon Man Shim

发明人： Cheon Man Shim

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05624 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/30105 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48

摘要： A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer.

摘要翻译： 闪存器件可以包括在基底上的基底绝缘层上的第一绝缘层，填充第一绝缘层中的沟槽的下线层，在第一绝缘层上依次层叠的第一绝缘层和第二绝缘层 下层导线层，填充第二绝缘层中的沟槽的中间线层，以及依次层叠在中间线层上的第二绝缘层和上层层，其中，下部导线层。 中间线层和上部线层可以彼此电连接，并且第一绝缘层可以包括与基底绝缘层接触的低k层。 此外，第一绝缘中间层，第二绝缘层和第二绝缘中间层中的每一个可以包括FSG层。

公开(公告)号：US07842985B2

公开(公告)日：2010-11-30

申请号：US11611915

申请日：2006-12-18

申请人： Keun Hyuk Lim

发明人： Keun Hyuk Lim

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14603 ,  H01L27/14643 ,  H01L27/14689

摘要： Disclosed is a CMOS image sensor including a gate electrode of a finger type transfer transistor for controlling the saturation state of a floating diffusion region according to the luminance level (i.e. low luminance or high luminance). The CMOS image sensor includes first and second photodiode regions for generating electrons in response to incident light, and a transfer transistor positioned between the first and second photodiodes for receiving the generated electrons transferred from the first and/or second photodiode.

摘要翻译： 公开了一种CMOS图像传感器，其包括用于根据亮度级（即，低亮度或高亮度）来控制浮动扩散区域的饱和状态的手指式转移晶体管的栅电极。 CMOS图像传感器包括用于响应于入射光而产生电子的第一和第二光电二极管区域，以及位于第一和第二光电二极管之间的传输晶体管，用于接收从第一和/或第二光电二极管转移的产生的电子。

公开(公告)号：US07838378B2

公开(公告)日：2010-11-23

申请号：US11896206

申请日：2007-08-30

申请人： Kwang Young Ko

发明人： Kwang Young Ko

IPC分类号： H01L21/331

CPC分类号： H01L29/735 ,  H01L29/1008 ,  H01L29/6625

摘要： A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an emitter region of the second conductivity type into the base region; forming an emitter in the emitter region, and forming a collector in the collector region; and forming a base in the semiconductor substrate through implanting high concentration impurity ions of the first conductive type into the semiconductor substrate.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 该方法包括在第一导电类型的半导体衬底中形成第二导电类型的集电极区域; 在所述集电极区域中形成所述第一导电类型的基极区域，并将所述第二导电类型的发射极区域形成为所述基极区域; 在发射极区域形成发射极，在集电极区域形成集电极; 以及通过将所述第一导电类型的高浓度杂质离子注入所述半导体衬底而在所述半导体衬底中形成基底。

公开(公告)号：US07829968B2

公开(公告)日：2010-11-09

申请号：US11847605

申请日：2007-08-30

申请人： Young-Je Yun

发明人： Young-Je Yun

IPC分类号： H01L31/0216

CPC分类号： H01L27/14627 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14685

摘要： An image sensor formed using a method for manufacturing a planar layer in a process for forming microlenses may be used in a complementary metal oxide semiconductor (CMOS) image sensor. Embodiments provide a planar layer that can improve the operation performance of an image sensor, a manufacturing method thereof, and the image sensor including the planar layer. Embodiments relate to a planar layer located under microlenses, the planar layer including valleys of patterns having a predetermined size, which may eliminate optical cross talk between adjacent pixels.

摘要翻译： 在互补金属氧化物半导体（CMOS）图像传感器中可以使用在用于形成微透镜的工艺中用于制造平面层的方法形成的图像传感器。 实施例提供了可以改善图像传感器的操作性能的平面层，其制造方法和包括平面层的图像传感器。 实施例涉及位于微透镜下的平面层，平面层包括具有预定尺寸的图案谷，其可以消除相邻像素之间的光学串扰。