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公开(公告)号:US06297676B1
公开(公告)日:2001-10-02
申请号:US09692985
申请日:2000-10-23
申请人: John W. Simmons , John J. Parkes , Manbir Nag
发明人: John W. Simmons , John J. Parkes , Manbir Nag
IPC分类号: H03B100
CPC分类号: H03K17/167
摘要: A ring inhibiting charging and discharging circuit (100) for use with an amplification circuit (102) that drives a load (108) is responsive to an input (104) and is capable of generating an output (106) corresponding to the input (104). The ring inhibiting charging and discharging circuit (100) includes a charge element (120) that is responsive to the output (112) from the amplification circuit (102). The charge element (120) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (130) is responsive to the output (106) from the amplification circuit (102) and includes a feedback circuit (132) and a staging circuit (134). The feedback circuit (132) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage. The staging circuit (134) is responsive to difference signal and gradually reduces the rate at which the load (108) is discharged over a preselected period of time once the difference signal indicates that the output voltage is within a preselected range of the input voltage.
摘要翻译: 用于与驱动负载(108)的放大电路(102)一起使用的环形抑制充电和放电电路(100)响应于输入(104)并且能够产生对应于输入(104)的输出(106) )。 禁止充电和放电电路(100)包括响应于来自放大电路(102)的输出(112)的电荷元件(120)。 当输入电压大于输出电压的预选倍数时,充电元件(120)能够对负载充电。 放电电路(130)响应来自放大电路(102)的输出(106)并且包括反馈电路(132)和分级电路(134)。 当输出电压小于输入电压的预选倍数时,反馈电路(132)断言差分信号。 一旦差分信号表示输出电压在输入电压的预选范围内,分级电路(134)响应差分信号并逐渐降低负载(108)在预选时间段内放电的速率。
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公开(公告)号:US06265913B1
公开(公告)日:2001-07-24
申请号:US09387095
申请日:1999-09-01
申请人: Dong-yun Lee , Seung-wook Lee , Wen-Chun Kim
发明人: Dong-yun Lee , Seung-wook Lee , Wen-Chun Kim
IPC分类号: H03B100
CPC分类号: H03K19/00361 , H03K17/167
摘要: Load driving circuits are adjusted to drive loads with fewer or more pull-down devices by sensing the load electrically coupled to the load driving circuit. In particular, capacitance of the load is compared to a threshold capacitance. If the capacitance of the load is less than the threshold capacitance, selected ones of the pull-down devices are disabled, thereby reducing the capacity of the load driving circuit. If the capacitance of the load is greater than the threshold capacitance, selected ones of the pull-down devices are enabled, thereby increasing the capacity of the load driving circuit. The pull-down devices include delay circuits that enable selected transistors after a delay.
摘要翻译: 调整负载驱动电路以通过感测电耦合到负载驱动电路的负载来驱动具有更少或更多下拉装置的负载。 特别地,将负载的电容与阈值电容进行比较。 如果负载的电容小于阈值电容,则选择的下拉装置被禁用,从而降低了负载驱动电路的容量。 如果负载的电容大于阈值电容,则选择的下拉器件被使能,从而增加负载驱动电路的容量。 下拉器件包括在延迟之后使得所选晶体管能够实现的延迟电路。
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公开(公告)号:US6160325A
公开(公告)日:2000-12-12
申请号:US232005
申请日:1999-01-14
申请人: Simon Turvey
发明人: Simon Turvey
CPC分类号: H02J13/00 , H03K17/167 , H03K17/302 , Y10T307/826
摘要: A power switching circuit includes first and second semiconductor switches providing parallel paths connecting a load across a power supply. A circuit maintains the second switch in an off state except when the current in the first switch exceeds a predetermined value.
摘要翻译: 电源开关电路包括第一和第二半导体开关,其提供连接跨过电源的负载的并行路径。 电路将第二开关维持在关闭状态,除了当第一开关中的电流超过预定值时。
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公开(公告)号:US6124747A
公开(公告)日:2000-09-26
申请号:US159546
申请日:1998-09-24
申请人: Koji Nasu
发明人: Koji Nasu
IPC分类号: H03K19/0175 , H03K17/16 , H03K19/003
CPC分类号: H03K19/00361 , H03K17/167
摘要: An output buffer circuit capable of controlling a through rate at a constant rate. Each decision circuit of a plurality of decision circuits (11-13, 18-20) receives a voltage potential from an output terminal (10) and compares it with a respective predetermined voltage value. Flip flops (15-17) with an asynchronous set function or flip flops (22-24) with an asynchronous reset function receive respective comparison results as decision results when receiving a respective trigger signal from a respective delay circuit from a plurality of delay circuits (14, 21) after the elapse of a respective predetermined time period from a time at which an input terminal (1) receives a H level control signal or an L level control signal. The flip flops (15-17 and 22-24) control the operation of output transistors (3-5 and 7-9) based on the respective decision results.
摘要翻译: 一种能够以恒定速率控制通过速率的输出缓冲电路。 多个判定电路(11-13,18-20)的判定电路从输出端子(10)接收电压电位,并将其与相应的预定电压值进行比较。 具有异步设置功能的触发器(15-17)或具有异步复位功能的触发器(22-24)在从多个延迟电路接收来自相应延迟电路的相应触发信号时作为判定结果接收相应的比较结果( 在从输入端子(1)接收到H电平控制信号或L电平控制信号的时间开始经过相应的预定时间段之后, 触发器(15-17和22-24)基于相应的判定结果控制输出晶体管(3-5和7-9)的操作。
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公开(公告)号:US6118311A
公开(公告)日:2000-09-12
申请号:US281068
申请日:1999-03-09
申请人: Hiroshi Kamiya
发明人: Hiroshi Kamiya
IPC分类号: H02H7/20 , H03K17/16 , H03K17/687 , H03K19/0175 , H03B1/00
CPC分类号: H03K17/167
摘要: In an output circuit including first and second power supply terminals, an input terminal, an output terminal, a first switching element connected between the first power supply terminal and the output terminal and being controlled by an input voltage at the input terminal, and a plurality of second switching elements connected in parallel between the output terminal and the second power supply terminal and being controlled by the input voltage, a third switching element is connected between the output terminal and one of the second switching elements, and a control circuit is rat provided for controlling the third switching element in accordance with an output voltage at the output terminal.
摘要翻译: 在包括第一和第二电源端子的输出电路中,输入端子,输出端子,连接在第一电源端子和输出端子之间并由输入端子处的输入电压控制的第一开关元件,以及多个 的第二开关元件并联连接在输出端子和第二电源端子之间并被输入电压控制,第三开关元件连接在输出端子和其中一个第二开关元件之间,并且提供控制电路 用于根据输出端子处的输出电压来控制第三开关元件。
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公开(公告)号:US6072335A
公开(公告)日:2000-06-06
申请号:US972791
申请日:1997-11-18
申请人: Peter William Hughes
发明人: Peter William Hughes
IPC分类号: H04N9/64 , G05F3/24 , H03K5/151 , H03K17/042 , H03K17/16 , H03K19/0175 , H03K19/0948 , H03K19/0185
CPC分类号: G05F3/24 , H03K17/04206 , H03K17/167 , H03K5/151
摘要: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.
摘要翻译: 输出电流单元包括具有连接在电压供应线和互补输出之间的第一晶体管的共源共栅电路。 第二和第三晶体管由在输出节点和接地线之间具有并联导电路径的反相器电路控制,并联导电路径具有与控制电路不同的载流能力,以切换电流承载路径中较强的电流。
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公开(公告)号:US5801550A
公开(公告)日:1998-09-01
申请号:US564499
申请日:1995-11-29
申请人: Yasunori Tanaka , Ikue Yamamoto
发明人: Yasunori Tanaka , Ikue Yamamoto
IPC分类号: H03K19/0175 , H03K17/16
CPC分类号: H03K17/167
摘要: The pulse output circuit device comprises two transistors (2, 4) for constructing an output buffer, a transistor (7) connected between the output line (OUTP) of the output buffer and the high potential supply voltage (VDD), a transistor (8) connected between the output line (OUT) of the output buffer and the low potential supply voltage (GND), a control circuit (39) for applying a gate signal to the transistor (7), and a control circuit (40) for applying a gate signal to the transistor (8). Whenever the signal level of the output buffer changes, the two control circuits (39, 40) turn on the transistor (7) or the transistor (8) for sharp level transition at the start of level transition, but turn on the transistor (7) or the transistor (8) on the basis of the relationship between the output level of the control circuit (39, 40) and the operating point of the transistor (7) or the transistor (8) at the end of level transition for absorption of the charge and discharge current to and from a parasitic capacitance (27). In the pulse output circuit device, it is possible to effectively prevent overshoot and undershoot caused when a pulse signal is outputted therethrough, while keeping the high output response speed and without increasing the circuit area.
摘要翻译: 脉冲输出电路装置包括用于构成输出缓冲器的两个晶体管(2,4),连接在输出缓冲器的输出线(OUTP)和高电位电源电压(VDD)之间的晶体管(7),晶体管(8) ),连接在输出缓冲器的输出线(OUT)和低电位电源电压(GND)之间,控制电路(39),用于向晶体管(7)施加栅极信号;以及控制电路(40) 到晶体管(8)的栅极信号。 每当输出缓冲器的信号电平变化时,两个控制电路(39,40)在电平转换开始时导通晶体管(7)或晶体管(8)以进行尖锐的电平转换,而导通晶体管(7 )或晶体管(8),基于控制电路(39,40)的输出电平与晶体管(7)或晶体管(8)在电平转换结束时的吸收的操作点之间的关系 的来自寄生电容(27)的充放电电流。 在脉冲输出电路装置中,在保持高输出响应速度且不增加电路面积的同时,可以有效地防止在输出脉冲信号时引起的过冲和下冲。
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公开(公告)号:US5448182A
公开(公告)日:1995-09-05
申请号:US236819
申请日:1994-05-02
申请人: Roger S. Countryman , Sunil Khatri
发明人: Roger S. Countryman , Sunil Khatri
IPC分类号: H03K17/16
CPC分类号: H03K17/167
摘要: A CMOS driver circuit (20) has a high impedance driver (30) and a low impedance driver (36) connected to the near end of a transmission line (43). The output impedance of the high impedance driver (30) matches the characteristic impedance of the transmission line (43). As a digital signal from the CMOS driver circuit (20) transitions from one logic state to another, the low impedance driver (30) drives the transmission line (43) until a predetermined voltage before the signal reaches its steady state voltage. A sensing circuit (24) senses when the predetermined voltage is reached, and in response, provides a control signal to deactivate the low impedance driver (36). The high impedance driver (30) completes the signal transition. The high impedance driver (30) absorbs the reflected waves from the far end of the transmission line (43), reducing the effects of ringing, and increasing noise immunity.
摘要翻译: CMOS驱动器电路(20)具有连接到传输线(43)的近端的高阻抗驱动器(30)和低阻抗驱动器(36)。 高阻抗驱动器(30)的输出阻抗匹配传输线(43)的特性阻抗。 当来自CMOS驱动器电路(20)的数字信号从一个逻辑状态转变到另一逻辑状态时,低阻抗驱动器(30)驱动传输线(43)直到信号达到其稳定状态电压之前的预定电压。 感测电路(24)感测何时到达预定电压,并且作为响应,提供控制信号以停用低阻抗驱动器(36)。 高阻抗驱动器(30)完成信号转换。 高阻抗驱动器(30)吸收来自传输线(43)的远端的反射波,减少了振铃的影响,并提高了抗噪声能力。
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公开(公告)号:US5289051A
公开(公告)日:1994-02-22
申请号:US950195
申请日:1992-09-24
申请人: Heinz Zitta
发明人: Heinz Zitta
CPC分类号: H03K17/163 , H03K17/167
摘要: An assembly has an MOS power transistor with an output circuit and an input circuit, a load connected in series with the output circuit of the MOS power transistor, and a control stage for controlling the input circuit of the MOS power transistor. A circuit configuration for triggering the MOS power transistor includes a constant current source and a switchable auxiliary current source connected parallel to the constant current source for feeding the control stage. The auxiliary current source is turned off at a predetermined period of time after an onset of a control event for the MOS power transistor.
摘要翻译: 组件具有MOS功率晶体管,其具有输出电路和输入电路,与MOS功率晶体管的输出电路串联的负载以及用于控制MOS功率晶体管的输入电路的控制级。 用于触发MOS功率晶体管的电路配置包括恒流源和与恒流源并联连接的用于馈送控制级的可切换辅助电流源。 辅助电流源在MOS功率晶体管的控制事件开始之后的预定时间段被关断。
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公开(公告)号:US11863167B1
公开(公告)日:2024-01-02
申请号:US17966882
申请日:2022-10-16
发明人: Jianye Qiu
IPC分类号: H03K17/16
CPC分类号: H03K17/167 , H03K2217/009 , H03K2217/0081
摘要: A drive circuit for a power switching transistor includes a first pull-up drive transistor connected in parallel with a second pull-up drive transistor, a first pull-down drive transistor coupled to the first and second pull-up drive transistors in series to drive the power switching transistor. When control signal is at a high level, the first pull-up driver is turned on, and the first pull-down driver is turned off. The second pull-up drive transistor being in turn-on or turn-off state is determined by comparing voltage of the power supply with the threshold value. When voltage of the power supply is lower than the threshold value, the first and second pull-up drive transistor are driven together. When voltage of the power supply is higher than the threshold value, the second pull-up driving transistor is turned on only after the driving output is slightly larger than the Miller plateau voltage.
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