公开(公告)号：US08165243B2

公开(公告)日：2012-04-24

申请号：US12801610

申请日：2010-06-17

申请人： John W. McCorkle

发明人： John W. McCorkle

IPC分类号： H04L27/00 ,  G06F7/44

CPC分类号： H04L27/2071 ,  H04B1/7172 ,  H04B1/7174 ,  H04B2201/71636 ,  H04L25/03834

摘要： A method (1300) is provided for generating one or more waveforms (130, 140). The method includes: generating a first toggle signal (1130, 1330) in response to a clock signal (1110), the first toggle signal having one of a first positive shape, a null shape, and a first negative shape for each cycle of the clock signal; multiplying the first toggle signal by a first coefficient signal to create a first intermediate signal (1440); generating a second toggle signal (1140, 1330) in response to the clock signal, the second toggle signal having one of a second positive shape, the null shape, and a second negative shape for each cycle of the clock signal; multiplying the second toggle signal by a second coefficient signal to create a second intermediate signal (1440); and generating a first output signal (1170) by adding the first intermediate signal and the second intermediate signal together (1350).

摘要翻译： 提供了一种用于产生一个或多个波形（130,140）的方法（1300）。 该方法包括：响应于时钟信号（1110）产生第一触发信号（1130,1330），第一触发信号具有第一触发信号（1110）的每个周期的第一正形状，零形状和第一负形状之一 时钟信号; 将第一触发信号乘以第一系数信号以产生第一中间信号（1440）; 响应于所述时钟信号产生第二触发信号（1140,1330），所述第二触发信号具有所述时钟信号的每个周期的第二正形状，零形状和第二负形状之一; 将所述第二触发信号乘以第二系数信号以产生第二中间信号（1440）; 以及通过将所述第一中间信号和所述第二中间信号相加来产生第一输出信号（1170）（1350）。

公开(公告)号：US08069200B2

公开(公告)日：2011-11-29

申请号：US11380613

申请日：2006-04-27

申请人： George Landers ,  Earle Jennings

发明人： George Landers ,  Earle Jennings

IPC分类号： G06F7/38 ,  G06F7/42 ,  G06F7/44 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC分类号： G06F7/485 ,  G06F5/012

摘要： A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.

摘要翻译： 与FP加法器一起使用的浮点（FP）移位器，提供移位的FP操作数作为指数基数（通常为2）乘以FP操作数的幂。 使用FP加法器的至少一个FP移位器的第一算术处理器。 FP加法器，用于产生FP结果的N个FP操作数，其中N至少为3。 第二运算处理器包括用于N个操作数的至少一个FP加法器。 FP移位器和FP加法器的描述，用于实现其操作方法。 FP移位器和FP加法器的实现。

公开(公告)号：US07915943B2

公开(公告)日：2011-03-29

申请号：US12522647

申请日：2008-01-09

申请人： Tetsuaki Yotsuji

发明人： Tetsuaki Yotsuji

IPC分类号： G06F7/44 ,  G06F7/16

CPC分类号： H03D7/1441 ,  H03D2200/0043 ,  H03D2200/0074 ,  H03D2200/0084

摘要： Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads.

摘要翻译： 关于N沟道第一晶体管和P沟道第二晶体管，它们的第一端子彼此连接，并且它们的第二端子彼此连接。 关于第三晶体管和第四晶体管，它们的第一端子也彼此连接，并且它们的第二端子也彼此连接。 对于通过第四晶体管的第一晶体管，提供通过用于耦合的第四电容器的第一电容器。 通过第四阻抗元件的第一阻抗元件设置在偏置电压通过第四晶体管施加到第一晶体管的路径中。 在第一第四晶体管的第一端子和第一输入端子之间提供第五电容器。 提供第五阻抗元件和第六阻抗元件作为差分对负载。

公开(公告)号：US07839199B2

公开(公告)日：2010-11-23

申请号：US12356402

申请日：2009-01-20

申请人： Chien-Nan Kuo ,  Huan-Sheng Chen

发明人： Chien-Nan Kuo ,  Huan-Sheng Chen

IPC分类号： G06F7/44

CPC分类号： G06F7/68

摘要： A circuit and a method for implementing frequency tripled I/Q signals are proposed, including receiving two input I/Q signals through frequency multipliers so as to generate two frequency multiplied signals and mixing the input I/Q signals and the corresponding frequency multiplied signals through mixers for generating and outputting two I/Q signals with a frequency three times that of the input I/Q signals. The invention eliminates the requirement for high amplitude of the input signals as in the prior art and has lower power consumption and broader bandwidth and can be used as high frequency signal sources in any single chip processes.

摘要翻译： 提出了一种用于实现三倍频I / Q信号的电路和方法，包括通过频率乘法器接收两个输入I / Q信号，以产生两个倍频信号，并将输入的I / Q信号和相应的倍频信号通过 用于产生和输出三倍于输入I / Q信号频率的两个I / Q信号的混频器。 本发明消除了如现有技术中对输入信号的高幅度的要求，并且具有较低的功耗和更宽的带宽，并且可以在任何单个芯片工艺中用作高频信号源。

公开(公告)号：US07831652B2

公开(公告)日：2010-11-09

申请号：US10035580

申请日：2001-12-28

申请人： Guy L. Steele, Jr.

发明人： Guy L. Steele, Jr.

IPC分类号： G06F7/44 ,  G06F7/00

CPC分类号： G06F9/30094 ,  G06F5/012 ,  G06F5/015 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/4876 ,  G06F7/49905 ,  G06F7/49942 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/3861 ,  G06F9/3885

摘要： A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand. Additionally, the results circuit provides a resulting status embedded within the resulting floating point operand.

摘要翻译： 一种用于提供浮点乘积的系统，包括：分析器电路，被配置为基于所述第一浮点数操作数内的数据和所述第二浮点内的数据来确定第一浮点操作数的第一状态和第二浮点操作数的第二状态 操作数。 此外，该系统包括耦合到分析器电路的结果电路。 结果电路被配置为断言包含第一个浮点数操作数和第二个浮点操作数的积的浮点运算数。 另外，结果电路提供嵌入到所得到的浮点运算数中的结果状态。

公开(公告)号：US20100235414A1

公开(公告)日：2010-09-16

申请号：US12714992

申请日：2010-03-01

申请人： Miaoqing Huang ,  Krzysztof Gaj

发明人： Miaoqing Huang ,  Krzysztof Gaj

IPC分类号： G06F7/44 ,  G06F5/01 ,  G06F7/72 ,  G06F7/42

CPC分类号： G06F7/728

摘要： A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of length w−1 from a preceding processing element as w−1 least significant bits. The most significant bit is configured as either zero or one. Then, two partial sums are calculated using a word of the operand Y, a word of the modulus M, a bit of the operand X, and the two intermediate partial sums. In a second clock cycle, a selection bit is obtained from a subsequent processing element and one of the two partial sums is selected based on the value of the selection bit. Then, the selected partial sum is used for calculation of a word of the Montgomery product.

摘要翻译： 蒙哥马利乘法装置相对于模数M计算操作数X和操作数Y的蒙哥马利乘积，并且包括多个处理要素。 在第一时钟周期中，通过从前一处理元件获得长度w-1的输入作为w-1个最低有效位来创建两个中间部分和。 最高有效位被配置为零或一。 然后，使用操作数Y的字，模M的字，操作数X的位和两个中间部分和来计算两个部分和。 在第二时钟周期中，从后续处理元件获得选择位，并且基于选择位的值选择两个部分和之一。 然后，所选择的部分和用于计算蒙哥马利产品的单词。

公开(公告)号：US07728624B2

公开(公告)日：2010-06-01

申请号：US11546011

申请日：2006-10-10

申请人： Gert Umbach

发明人： Gert Umbach

IPC分类号： H03K19/094 ,  G06F7/38 ,  H03K19/173 ,  H01L25/00 ,  H03K19/00 ,  G06F7/44

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.

摘要翻译： 一种包括至少一个组的集成电路，包括以子组布置的多个算术/逻辑单元。 在多个算术/逻辑单元的输入处的子组中，在每种情况下，第一选择单元中的单个单元连接在输入侧，其中没有其他选择单元直接连接在该选择单元的输入侧。 第一选择单元彼此耦合，使得可以实现组内的算术/逻辑单元和/或算术/逻辑单元与上游组的逻辑互连的水平和/或垂直逻辑互连。 在每种情况下，第二选择单元连接在算术/逻辑单元列的输出侧。 组的第二选择单元在输出侧连接到每个一个总线，并且微处理器耦合到该总线。

公开(公告)号：US07710185B2

公开(公告)日：2010-05-04

申请号：US11569021

申请日：2005-05-12

申请人： Tajinder Manku

发明人： Tajinder Manku

IPC分类号： G06F7/44 ,  G06G7/16

CPC分类号： H03K5/1252 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03F1/3211 ,  H03F1/3223 ,  H03F3/24 ,  H03F3/45183 ,  H03F2200/372 ,  H03F2200/87 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03F2203/45498 ,  H03F2203/45544 ,  H03K5/02 ,  H04B1/0475 ,  H04B1/123 ,  H04B2001/0441

摘要： A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

摘要翻译： 提供了用于消除三阶互调的CMOS跨导体。 跨导体包括跨导电路和可调谐失真电路。 跨导电路采用输入电压并产生具有跨导元件和IM3元件的输出电流。 失真电路采用相同的输入电压，并产生具有与跨导电路的IM3元件相等幅度和相反相位的IM3元件的电流。 控制器电路调谐失真电路以将其IM3元件调整为基本上等于跨导电路的IM3的振幅。 失真和跨导电路被布置为对其输出电流求和，从而有效地消除IM3元件，从而使跨导相对未被修改。

公开(公告)号：US07613762B2

公开(公告)日：2009-11-03

申请号：US10035584

申请日：2001-12-28

申请人： Guy L. Steele, Jr.

发明人： Guy L. Steele, Jr.

IPC分类号： G06F7/44 ,  G06F7/00

CPC分类号： G06F7/4873 ,  G06F7/499

摘要： A system for providing a floating point remainder comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and the second floating point operand, respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the remainder of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

摘要翻译： 一种用于提供浮点余数的系统包括：分析器电路，被配置为基于第一浮点操作数和第二浮点操作数内的数据来确定第一浮点操作数的第一状态和第二浮点操作数的第二状态， 分别。 此外，该系统包括耦合到分析器电路的结果电路。 结果电路被配置为断言包含第一个浮点数操作数和第二个浮点操作数的剩余部分的结果浮点操作数，以及嵌入到生成的浮点操作数内的结果状态。

公开(公告)号：US20090256596A1

公开(公告)日：2009-10-15

申请号：US12400948

申请日：2009-03-10

申请人： Hyoung-seok Oh

发明人： Hyoung-seok Oh

IPC分类号： H03K21/00 ,  G06F7/44 ,  H03K3/289

CPC分类号： G06F7/68 ,  H03K3/356121 ,  H03K23/667

摘要： A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the first signal; and at least one switch unit that is switched in response to a control signal to modify a signal transfer path between the plurality of the flip-flops, wherein a different number of flip-flops are activated in response to each first and second status of the control signal so that the frequency of the first signal is divided by different multiples.

摘要翻译： 触发器，以及使用触发器的分频器和RF电路。 分频器，其接收第一信号并通过除以第一信号的频率产生第二信号，包括多个触发器，每个触发器基于第一信号锁存和输出信号; 以及响应于控制信号而被切换以修改多个触发器之间的信号传送路径的至少一个开关单元，其中不同数量的触发器响应于第一和第二状态 控制信号使第一信号的频率除以不同的倍数。