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    Trench gate depletion mode VDMOS device and method for manufacturing the same
    101.
    发明授权
    Trench gate depletion mode VDMOS device and method for manufacturing the same 有权

    公开(公告)号：US11387349B2

    公开(公告)日：2022-07-12

    申请号：US17265587

    申请日：2019-10-14

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Yan Gu ,  Shikang Cheng ,  Sen Zhang

    IPC: H01L29/66 ,  H01L29/78

    Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

    Integrated semiconductor device and electronic apparatus
    105.
    发明授权
    Integrated semiconductor device and electronic apparatus 有权

    公开(公告)号：US11276690B2

    公开(公告)日：2022-03-15

    申请号：US16755817

    申请日：2018-11-21

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

    IPC: H01L27/088 ,  H01L29/78

    Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

    LDMOS component, manufacturing method therefor, and electronic device
    106.
    发明授权
    LDMOS component, manufacturing method therefor, and electronic device 有权

    公开(公告)号：US11158737B2

    公开(公告)日：2021-10-26

    申请号：US16644856

    申请日：2018-08-03

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Huajun Jin ,  Guipeng Sun ,  Hongfeng Jin

    IPC: H01L29/78 ,  H01L29/66

    Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.

    TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREFOR
    107.
    发明申请
    TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREFOR 有权

    公开(公告)号：US20210287932A1

    公开(公告)日：2021-09-16

    申请号：US16483081

    申请日：2018-07-03

    Applicant: CSMC Technologies FAB2 Co., Ltd.

    Inventor： Shukun Ql

    IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/32 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/761

    Abstract: A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

    VDMOS DEVICE AND MANUFACTURING METHOD THEREFOR
    108.
    发明申请
    VDMOS DEVICE AND MANUFACTURING METHOD THEREFOR 有权

    公开(公告)号：US20210098606A1

    公开(公告)日：2021-04-01

    申请号：US17121360

    申请日：2020-12-14

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Zheng BIAN

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

    Abstract: A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

    MOSFET STRUCTURE, AND MANUFACTURING METHOD THEREOF
    110.
    发明申请
    MOSFET STRUCTURE, AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200295184A1

    公开(公告)日：2020-09-17

    申请号：US16890151

    申请日：2020-06-02

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Tse-Huang LO

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

    Abstract: A MOSFET structure and a manufacturing method thereof are provided. The structure includes a substrate, a well region of a first conductivity type, a first trench formed on a surface of the well region of the first conductivity type and extending downwards to a well region of a second conductivity type, a source disposed in the well region of the second conductivity type and under the first trench, a gate oxide layer disposed on an inner surface of the first trench, a polysilicon gate disposed on the gate oxide layer, a conductive plug extending downwards from above the first trench and being in contact with the well region of the second conductivity type after extending through the source, an insulation oxide layer filled in the first trench between the conductive plug and the polysilicon gate, and a drain disposed outside the first trench and obliquely above the source.

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