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1.发明申请公开(公告)号：US20200343845A1
公开(公告)日：2020-10-29
申请号：US16958868
申请日：2018-12-29
发明人： Rui ZHONG , Mingshu ZHANG , Sen ZHANG , Jinyu XIAO , Wei SU , Weifeng SUN , Longxing SHI
摘要： A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.
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公开(公告)号：US20220376094A1
公开(公告)日：2022-11-24
申请号：US17762212
申请日：2020-08-26
发明人： Long ZHANG , Jie MA , Yan GU , Sen ZHANG , Jing ZHU , Jinli GONG , Weifeng SUN , Longxing SHI
IPC分类号： H01L29/739 , H01L29/08 , H01L29/10 , H01L29/06
摘要： An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
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公开(公告)号：US20240222478A1
公开(公告)日：2024-07-04
申请号：US18558422
申请日：2022-01-24
IPC分类号： H01L29/739 , H01L27/07 , H01L29/423 , H01L29/866
CPC分类号： H01L29/7394 , H01L27/0727 , H01L29/4236 , H01L29/866
摘要： A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.
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公开(公告)号：US20230036341A1
公开(公告)日：2023-02-02
申请号：US17789628
申请日：2020-09-04
发明人： Jingchuan ZHAO , Zhili ZHANG , Sen ZHANG
摘要： Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.
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公开(公告)号：US20220336657A1
公开(公告)日：2022-10-20
申请号：US17620952
申请日：2020-05-26
发明人： Zhili ZHANG , Jingchuan ZHAO , Sen ZHANG
摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.
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公开(公告)号：US20200335607A1
公开(公告)日：2020-10-22
申请号：US16768563
申请日：2018-11-21
发明人： Shikang CHENG , Yan GU , Sen ZHANG
摘要： A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.
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7.发明申请公开(公告)号：US20190252537A1
公开(公告)日：2019-08-15
申请号：US16329413
申请日：2017-08-31
发明人： Yan GU , Shikang CHENG , Sen ZHANG
IPC分类号： H01L29/78 , H01L27/098 , H01L29/66
CPC分类号： H01L29/7803 , H01L27/02 , H01L27/06 , H01L27/098 , H01L29/06 , H01L29/66712
摘要： A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).
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公开(公告)号：US20180122921A1
公开(公告)日：2018-05-03
申请号：US15564172
申请日：2016-01-29
发明人： Shukun QI , Guangsheng ZHANG , Guipeng SUN , Sen ZHANG
CPC分类号： H01L29/66681 , H01L29/06 , H01L29/063 , H01L29/7816
摘要： Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).
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公开(公告)号：US20220367682A1
公开(公告)日：2022-11-17
申请号：US17765295
申请日：2020-08-18
发明人： Nailong HE , Sen ZHANG
IPC分类号： H01L29/66 , H01L29/78 , H01L21/04 , H01L21/762
摘要： A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.
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公开(公告)号：US20210175347A1
公开(公告)日：2021-06-10
申请号：US16770362
申请日：2018-12-05
发明人： Nailong HE , Sen ZHANG , Guangsheng ZHANG , Yun LAN
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78 , H01L21/762
摘要： A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.
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