中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

185 records (took 0.018 seconds)

    Power distribution network simulation method using variable reduction method
    101.
    发明授权
    Power distribution network simulation method using variable reduction method 失效
    配电网络仿真方法采用变量缩减法

    公开(公告)号：US07509596B2

    公开(公告)日：2009-03-24

    申请号：US11056955

    申请日：2005-02-11

    Applicant: Jong-Eun Koo ,  Kyung-Ho Lee ,  Young-Hoe Cheon

    Inventor： Jong-Eun Koo ,  Kyung-Ho Lee ,  Young-Hoe Cheon

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/509 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.

    Abstract translation: 一种能够快速准确地分析大型配电网络的配电网仿真方法。 在配电网络仿真方法中，通过使用可变减小方法将大的原始电路减小到合适的大小，获得了简化电路方程的解，并且基于原始电路方程的解 通过使用可变简化方法对减小电路的方程进行求解。 根据配电网仿真方法采用可变减速法，可以快速准确地分析大型配电网络。

    Method of fabricating heterojunction bipolar transistor
    102.
    发明授权
    Method of fabricating heterojunction bipolar transistor 有权
    异质结双极晶体管的制造方法

    公开(公告)号：US07273789B2

    公开(公告)日：2007-09-25

    申请号：US11227503

    申请日：2005-09-15

    Applicant: Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

    Inventor： Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

    IPC: H01L21/331

    CPC classification number: H01L29/66318 ,  H01L29/7371

    Abstract: Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.

    Abstract translation: 提供了一种制造异质结双极晶体管（HBT）的方法。 该方法包括：在衬底上依次沉积副集电极层，集电极层，基极层，发射极层和发射极覆盖层; 在发射极盖层上形成发射电极; 通过使用发射极电极作为蚀刻掩模，分别在垂直和负向倾斜的方向上依次蚀刻发射极覆盖层和发射极层来形成台面型发射极以暴露基底层; 以及使用发射电极作为与发射极电极自对准的掩模，在所述暴露的基底层上形成基极。 在这种方法中，台面型发射极和基极之间的距离可以被最小化并可重复地控制。 此外，可以实现具有优异的高频特性的自对准装置。

    Power distribution network simulation method using variable reduction method
    104.
    发明申请
    Power distribution network simulation method using variable reduction method 失效
    配电网络仿真方法采用变量缩减法

    公开(公告)号：US20050203722A1

    公开(公告)日：2005-09-15

    申请号：US11056955

    申请日：2005-02-11

    Applicant: Jong-Eun Koo ,  Kyung-Ho Lee ,  Young-Hoe Cheon

    Inventor： Jong-Eun Koo ,  Kyung-Ho Lee ,  Young-Hoe Cheon

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/509 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.

    Abstract translation: 一种能够快速准确地分析大型配电网络的配电网仿真方法。 在配电网络仿真方法中，通过使用可变减小方法将大的原始电路减小到合适的大小，获得了简化电路方程的解，并且基于原始电路方程的解 通过使用可变简化方法对减小电路的方程进行求解。 根据配电网仿真方法采用可变减速法，可以快速准确地分析大型配电网络。

    Backside illuminated image sensor and method of manufacturing the same
    108.
    发明授权
    Backside illuminated image sensor and method of manufacturing the same 有权
    背面照明图像传感器及其制造方法

    公开(公告)号：US09034682B2

    公开(公告)日：2015-05-19

    申请号：US13177253

    申请日：2011-07-06

    Applicant: Eun-Sub Shim ,  Jung-Chak Ahn ,  Bum-Suk Kim ,  Kyung-Ho Lee

    Inventor： Eun-Sub Shim ,  Jung-Chak Ahn ,  Bum-Suk Kim ,  Kyung-Ho Lee

    IPC: H01L31/0232 ,  H01L27/146

    CPC classification number: H01L27/1464 ,  H01L27/14625 ,  H01L27/14685 ,  H01L27/14687

    Abstract: A method of manufacturing a backside illuminated image sensor, including forming a first isolation layer in a first semiconductor layer, such that the first isolation layer defines pixels of a pixel array in the first semiconductor layer, forming a second semiconductor layer on a first surface of the first semiconductor layer, forming a second isolation layer in the second semiconductor layer, such that the second isolation layer defines active device regions in the second semiconductor layer, forming photo detectors and circuit devices by implanting impurities into a first surface of the second semiconductor layer, the first surface of the second semiconductor layer facing away from the first semiconductor layer, forming a wiring layer on the first surface of the second semiconductor layer, and forming a light filter layer on a second surface of the first semiconductor layer.

    Abstract translation: 一种制造背面照射图像传感器的方法，包括在第一半导体层中形成第一隔离层，使得第一隔离层限定第一半导体层中的像素阵列的像素，在第一半导体层的第一表面上形成第二半导体层 所述第一半导体层在所述第二半导体层中形成第二隔离层，使得所述第二隔离层限定所述第二半导体层中的有源器件区域，通过将杂质注入到所述第二半导体层的第一表面中来形成光检测器和电路器件 所述第二半导体层的第一表面背离所述第一半导体层，在所述第二半导体层的所述第一表面上形成布线层，并且在所述第一半导体层的第二表面上形成滤光器层。

    Unit pixel array and image sensor having the same
    109.
    发明授权
    Unit pixel array and image sensor having the same 有权
    单位像素阵列和具有相同像素的图像传感器

    公开(公告)号：US08970768B2

    公开(公告)日：2015-03-03

    申请号：US13218550

    申请日：2011-08-26

    Applicant: Jung-Chak Ahn ,  Bum-Suk Kim ,  Kyung-Ho Lee ,  Eun-Sub Shim

    Inventor： Jung-Chak Ahn ,  Bum-Suk Kim ,  Kyung-Ho Lee ,  Eun-Sub Shim

    IPC: H04N9/083 ,  H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N5/225 ,  H01L31/062 ,  H01L31/113 ,  H01L21/00 ,  H01L27/146

    CPC classification number: H01L27/14629 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464

    Abstract: A unit pixel array of an image sensor includes a semiconductor substrate having a plurality of unit pixels, an interlayer insulating layer disposed on a front side of the semiconductor substrate, a plurality of color filters disposed on a back side of the semiconductor substrate, a plurality of light path converters, each of the light path converters being disposed adjacent to at least one color filter and having a pair of slanted side edges extending from opposing ends of a horizontal bottom edge, and a plurality of micro lenses disposed on the color filters.

    Abstract translation: 图像传感器的单位像素阵列包括具有多个单位像素的半导体衬底，设置在半导体衬底的前侧的层间绝缘层，设置在半导体衬底背面的多个滤色器，多个 每个光路转换器设置成与至少一个滤色器相邻，并且具有从水平底部边缘的相对端延伸的一对倾斜侧边缘和设置在滤色器上的多个微透镜。

Patent Agency Ranking