公开(公告)号：US20120153361A1

公开(公告)日：2012-06-21

申请号：US13307069

申请日：2011-11-30

申请人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01L21/283 ,  H01L29/808

CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

摘要： Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

摘要翻译： 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20120142148A1

公开(公告)日：2012-06-07

申请号：US13283626

申请日：2011-10-28

申请人： Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

发明人： Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

IPC分类号： H01L21/335

CPC分类号： H01L29/7783 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

摘要翻译： 提供一种制造常闭型高频器件结构的方法以及在单个衬底上同时制造常开模式高频器件结构和常关型高频器件结构的方法。

公开(公告)号：US08130041B2

公开(公告)日：2012-03-06

申请号：US12960153

申请日：2010-12-03

申请人： Seong-Il Kim ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Seong-Il Kim ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H03F3/68

CPC分类号： H03F3/245 ,  H03F1/0261 ,  H03F1/52 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/18 ,  H03F2200/451

摘要： Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.

摘要翻译： 提供了一种功率放大器装置。 功率放大器装置包括：切断单元，切断从信号输入端子发送的信号的直流（DC）分量; 连接到所述切断单元的电路保护单元，并且稳定从所述切断单元传送的信号; 以及放大单元，连接到所述电路保护单元并放大从所述电路保护单元传送的信号，其中所述放大单元包括与所述电路保护单元并联连接的多个晶体管，所述电路保护单元包括电阻器， 多个晶体管。

公开(公告)号：US07986211B2

公开(公告)日：2011-07-26

申请号：US12968022

申请日：2010-12-14

申请人： Seong-il Kim ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Seong-il Kim ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F2017/0086 ,  H01L28/10

摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.

摘要翻译： 提供一种电感器。 电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子 形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线 连接到第一至第四导电端子中的第一和第三导电端子。

公开(公告)号：US07273789B2

公开(公告)日：2007-09-25

申请号：US11227503

申请日：2005-09-15

申请人： Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

发明人： Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

IPC分类号： H01L21/331

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.

摘要翻译： 提供了一种制造异质结双极晶体管（HBT）的方法。 该方法包括：在衬底上依次沉积副集电极层，集电极层，基极层，发射极层和发射极覆盖层; 在发射极盖层上形成发射电极; 通过使用发射极电极作为蚀刻掩模，分别在垂直和负向倾斜的方向上依次蚀刻发射极覆盖层和发射极层来形成台面型发射极以暴露基底层; 以及使用发射电极作为与发射极电极自对准的掩模，在所述暴露的基底层上形成基极。 在这种方法中，台面型发射极和基极之间的距离可以被最小化并可重复地控制。 此外，可以实现具有优异的高频特性的自对准装置。

公开(公告)号：US08338241B2

公开(公告)日：2012-12-25

申请号：US13283626

申请日：2011-10-28

申请人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/7783 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

摘要翻译： 提供一种制造常闭型高频器件结构的方法以及在单个衬底上同时制造常开模式高频器件结构和常关型高频器件结构的方法。

公开(公告)号：US20110140825A1

公开(公告)日：2011-06-16

申请号：US12968022

申请日：2010-12-14

申请人： Seong-il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

发明人： Seong-il KIM ,  Jongmin Lee ,  Byoung-Gue Min ,  Hyung Sup Yoon ,  Hae Cheon Kim ,  Eun Soo Nam

IPC分类号： H01F27/30

CPC分类号： H01F17/0006 ,  H01F2017/0086 ,  H01L28/10

摘要： Provided is an inductor. The inductor includes a first to a fourth conductive terminals formed in one direction within a semiconductor substrate, a first conductive line formed on one side of the semiconductor substrate and electrically connected to the second and third conductive terminals interiorly positioned among the first to fourth conductive terminals, a second conductive line formed on the one side of the semiconductor substrate and electrically connected to the first and fourth conductive terminals exteriorly positioned among the first to fourth conductive terminals, and a third conductive line formed on the other side of the semiconductor substrate and electrically connected to the first and third conductive terminals among the first to fourth conductive terminals.

摘要翻译： 提供一种电感器。 电感器包括在半导体衬底内的一个方向上形成的第一至第四导电端子，形成在半导体衬底的一侧上的第一导电线，并且电连接到内部位于第一至第四导电端子之间的第二和第三导电端子 形成在所述半导体衬底的一侧上并与外部位于所述第一至第四导电端子之间的所述第一和第四导电端子电连接的第二导电线，以及形成在所述半导体衬底的另一侧上并电连接的第三导电线 连接到第一至第四导电端子中的第一和第三导电端子。

公开(公告)号：US07494909B2

公开(公告)日：2009-02-24

申请号：US11499116

申请日：2006-08-03

申请人： Chull Won Ju ,  Byoung Gue Min ,  Seong Il Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young Il Kang

发明人： Chull Won Ju ,  Byoung Gue Min ,  Seong Il Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young Il Kang

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/46 ,  H01L21/44 ,  H01L29/40 ,  H01L23/02

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

摘要翻译： 提供一种芯片，芯片堆叠及其制造方法。 多个芯片，每个芯片包括：形成在晶片上的至少一个焊盘; 并且从晶片的底部突出到预定厚度并且形成在露出焊盘底部的通孔中的金属层被堆叠成使得焊盘和相邻芯片的金属层接合。 这导致了简化的制造工艺，高芯片性能和用于芯片堆叠的小占地面积。

公开(公告)号：US08722474B2

公开(公告)日：2014-05-13

申请号：US13592589

申请日：2012-08-23

申请人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/338

CPC分类号： H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

摘要翻译： 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US20130146944A1

公开(公告)日：2013-06-13

申请号：US13592589

申请日：2012-08-23

申请人： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

摘要翻译： 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。