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    Method for building menus during idle times
    106.
    发明授权
    Method for building menus during idle times 失效
    空闲时间建立菜单的方法

    公开(公告)号：US6067087A

    公开(公告)日：2000-05-23

    申请号：US33922

    申请日：1998-03-03

    Applicant: Jeffrey Thomas Krauss ,  Ravindra Kumar Agrawal

    Inventor： Jeffrey Thomas Krauss ,  Ravindra Kumar Agrawal

    IPC: G06F3/0482 ,  G06F3/14 ,  G06F13/372

    CPC classification number: G06F3/0482

    Abstract: A Menu Building Component (MBC) builds menus during a computer's idle time. The MBC builds a menu for each menu title on a Menu Bar and stores each built menu in the computer's random access memory (RAM). The MBC requests an allocation of idle time by registering with a Component Manager. The Component Manager notifies the MBC of the availability of idle time by sending a notification signal to the MBC. When the MBC receives the notification signal, the MBC builds the next unbuilt menu corresponding to a menu title on the Menu Bar. When the last menu has been built, the MBC unregisters with the component manager. If a user makes a menu demand for an unbuilt menu, the MBC will build the demanded menu on demand, rather than during an idle time. If the user makes a menu demand for a built menu, the built menu is recalled from RAM and displayed for use by the user. Because the MBC builds menus during idle times, start-up delays and menu demand delays are minimized. By storing the built menus in RAM, the MBC can display menus instantaneously upon demand, with little or no delay perceivable to the user.

    Abstract translation: 菜单构建组件（MBC）在计算机空闲时间内构建菜单。 MBC在菜单栏上为每个菜单标题构建菜单，并将每个内置菜单存储在计算机的随机存取存储器（RAM）中。 MBC通过向组件管理器注册来请求分配空闲时间。 组件管理器通过向MBC发送通知信号来通知MBC空闲时间的可用性。 当MBC收到通知信号时，MBC将在菜单栏上构建与菜单标题对应的下一个未构建的菜单。 当最后一个菜单被构建时，MBC使用组件管理器注销。 如果用户对未建立的菜单进行菜单需求，则MBC将根据需要构建所需的菜单，而不是在空闲时间内。 如果用户对内置菜单进行菜单需求，则内置菜单从RAM中调用并显示供用户使用。 因为MBC在空闲时间内构建菜单，所以启动延迟和菜单需求延迟最小化。 通过将内建的菜单存储在RAM中，MBC可以根据需要瞬时显示菜单，对用户很少或根本没有延迟。

    Methods and system for predecoding instructions in a superscalar data processing system
    108.
    发明授权
    Methods and system for predecoding instructions in a superscalar data processing system 失效
    超标量数据处理系统中预解码指令的方法和系统

    公开(公告)号：US5828895A

    公开(公告)日：1998-10-27

    申请号：US531882

    申请日：1995-09-20

    Applicant: Kin Shing Chan ,  Ravindra Kumar Nair

    Inventor： Kin Shing Chan ,  Ravindra Kumar Nair

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

    CPC classification number: G06F9/382 ,  G06F9/30094 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

    Abstract: In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache. The predecode bits enable the dispatch unit to efficiently, and without fully decoding the instruction at dispatch time, select an execution unit for executing the instruction and determine if the data processing system resources required for execution of the instruction are available before the dispatch unit dispatches the instruction.

    Abstract translation: 响应于从主存储器重新加载用于存储在超标量数据处理系统中的指令高速缓存中的指令，从多个指令类别中选择指令所属的特定指令类别。 确定指令执行所需的数据处理系统资源的类型和所需的每种类型的资源的数量。 此后，计算多个解码位，其中解码位表示指令所属的特定指令类别以及执行指令所需的每个数据处理系统资源的类型和数量。 此后，指令和预解码位存储在指令高速缓存中。 预分解位使得调度单元能够有效地并且在调度时没有完全解码指令的情况下，选择用于执行指令的执行单元，并且在调度单元调度之前确定执行指令所需的数据处理系统资源是否可用 指令。

    Method and apparatus for managing the execution of instructons with proximate successive branches in a cache-based data processing system
    109.
    发明授权
    Method and apparatus for managing the execution of instructons with proximate successive branches in a cache-based data processing system 失效
    用于在基于高速缓存的数据处理系统中管理具有邻近连续分支的指令执行的方法和装置

    公开(公告)号：US5794027A

    公开(公告)日：1998-08-11

    申请号：US803649

    申请日：1997-02-21

    Applicant: Gregory Frederick Grohoski ,  Ravindra Kumar Nair

    Inventor： Gregory Frederick Grohoski ,  Ravindra Kumar Nair

    IPC: G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/3804

    Abstract: A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss occurs. When a prefetch miss occurs, the BAB is checked to see if instructions corresponding to the target address are available. If they are available, these instructions are copied into an appropriate buffer. If the instructions corresponding to the target address are unavailable, these instructions are fetched from the I-cache and placed into a buffer and, selectively, into the BAB. The BAB only maintains branch target addresses that have not been previously scanned and that cannot be prefetched in time. This allows for smaller buffer sizes, and resulting quicker access time, when checking the BAB for instructions to be executed by a processor.

    Abstract translation: 称为分支预期缓冲器（BAB）的小型缓冲器用于存储当发生指令预取缺失时可能从指令高速缓存（I-cache）需要的指令组。 当发生预取未命中时，检查BAB以查看与目标地址相对应的指令是否可用。 如果可用，这些指令将被复制到适当的缓冲区。 如果与目标地址相对应的指令不可用，则从I缓存中取出这些指令，并将其放入缓冲区，并有选择地放入BAB。 BAB仅维护尚未先前扫描并且不能及时预取的分支目标地址。 当检查BAB以获得由处理器执行的指令时，这允许较小的缓冲区大小，并导致更快的访问时间。

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