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公开(公告)号：US20200319876A1
公开(公告)日：2020-10-08
申请号：US16829280
申请日：2020-03-25
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
Abstract: A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.
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公开(公告)号：US20200272589A1
公开(公告)日：2020-08-27
申请号：US16874055
申请日：2020-05-14
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US10740267B1
公开(公告)日：2020-08-11
申请号：US16503243
申请日：2019-07-03
Inventor： Nirav Prashantkumar Trivedi , Sandip Atal , Rolf Nandlinger
Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
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公开(公告)号：US20190272211A1
公开(公告)日：2019-09-05
申请号：US16289425
申请日：2019-02-28
Applicant: STMicroelectronics Application GMBH
Inventor： Roberto Colombo
IPC: G06F11/07
Abstract: A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.
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公开(公告)号：US10375774B2
公开(公告)日：2019-08-06
申请号：US15216561
申请日：2016-07-21
Inventor： Manuel Gaertner , Sergio Lecce , Giovanni Luca Torrisi
Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.
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Patent Agency Ranking
106.发明申请公开(公告)号：US20180330123A1
公开(公告)日：2018-11-15
申请号：US15965802
申请日：2018-04-27
Inventor： Roberto COLOMBO , Nicolas BERNARD GROSSIER , Giovanni DISIRIO , Lorenzo RE FIORENTIN
CPC classification number: G06F21/71 , G06F11/0721 , G06F11/0751 , G06F11/0772 , G06F21/57 , G06F21/602 , G06F21/77 , H03K19/17728 , H04L9/0618 , H04L2209/12 , H04L2209/127
Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
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公开(公告)号：US20180329774A1
公开(公告)日：2018-11-15
申请号：US15975507
申请日：2018-05-09
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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108.发明授权公开(公告)号：US09992916B2
公开(公告)日：2018-06-05
申请号：US14595391
申请日：2015-01-13
Inventor： Giovanni Luca Torrisi , Domenico Massimo Porto , Sergio Lecce , Manuel Gaertner
CPC classification number: H05K7/20945 , H01L23/34 , H01L2924/0002 , H03K2017/0806 , Y10T307/773 , H01L2924/00
Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
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公开(公告)号：US09606611B2
公开(公告)日：2017-03-28
申请号：US14591779
申请日：2015-01-07
Applicant: STMicroelectronics Application GmbH
Inventor： Fred Rennig
IPC: G06F1/26 , G06F1/32 , H04L12/403
CPC classification number: G06F1/3243 , G06F1/3209 , G06F1/3234 , G06F1/3287 , G06F1/3293 , H04L12/403 , Y02D10/10
Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.
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110.发明申请公开(公告)号：US20130214724A1
公开(公告)日：2013-08-22
申请号：US13849374
申请日：2013-03-22
Applicant: STMicroelectronics Application GmbH
Inventor： Reiner Schwartz
IPC: H02J7/00
CPC classification number: H02J7/0019 , B60L11/1866 , B60L2240/547 , B60L2240/549 , H02J7/0016 , Y02T10/7005 , Y02T10/7061
Abstract: A method and an active battery balancing circuit for balancing an electric charge in a plurality of cells of a battery that are electrically connected in series is disclosed. A first subset of the cells of the battery is electrically connected to an inductance for providing a current flow from the first subset through the inductance. The first subset of the cells is disconnected from the inductance, and a current is allowed to flow from the inductance into a second subset of the cells of the battery. At least one of the first and the second subset of the cells of the battery comprises two or more cells.
Abstract translation: 公开了一种用于平衡串联电连接的电池的多个单电池中的电荷的方法和有源电池平衡电路。 电池的单元的第一子集电连接到电感，以提供来自第一子集的电流流过电感。 电池的第一子集与电感断开，并且允许电流从电感流入电池单元的第二子集。 电池单元的第一和第二子集中的至少一个包括两个或更多个单元。
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