公开(公告)号：US20070102714A1

公开(公告)日：2007-05-10

申请号：US11558113

申请日：2006-11-09

Applicant: Sung-Soo LEE ,  Un-Cheol SUNG ,  Sang-Pil LEE

Inventor： Sung-Soo LEE ,  Un-Cheol SUNG ,  Sang-Pil LEE

IPC: H01L33/00

CPC classification number: H01L51/5203 ,  H01L27/3211 ,  H01L2251/558

Abstract: The present invention discloses a display device having a substrate; a light emitting layer arranged on the substrate; a first electrode arranged on the light emitting layer; and a second electrode facing the first electrode, where the light emitting layer is arranged between the second electrode and the first electrode. A thickness of the first electrode varies depending on the wavelength of a light emitted from the light emitting layer.

Abstract translation: 本发明公开了一种具有基板的显示装置， 布置在所述基板上的发光层; 布置在所述发光层上的第一电极; 以及面对第一电极的第二电极，其中发光层布置在第二电极和第一电极之间。 第一电极的厚度根据从发光层发射的光的波长而变化。

公开(公告)号：US20060120172A1

公开(公告)日：2006-06-08

申请号：US11228189

申请日：2005-09-19

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C7/10

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract translation: 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US07024598B2

公开(公告)日：2006-04-04

申请号：US10003390

申请日：2001-10-30

Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

IPC: G06F11/00 ,  G11C29/00

CPC classification number: G11C29/44 ,  G11C29/40

Abstract: A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

公开(公告)号：US06971863B2

公开(公告)日：2005-12-06

申请号：US10320485

申请日：2002-12-17

Applicant: Kyung-soo Park ,  Tae-hyuk Kim ,  Hoon Chang ,  Sung-soo Lee

Inventor： Kyung-soo Park ,  Tae-hyuk Kim ,  Hoon Chang ,  Sung-soo Lee

IPC: H01L21/56 ,  B29C33/58 ,  B29C45/14 ,  B29C70/72

CPC classification number: B29C33/58 ,  H01L21/565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A molding apparatus for molding semiconductor devices using a molding compound in which a mold is automatically treated with a mold releasing agent is provided. A lead frame strip in-magazine part and a tablet loading part are designed so that dummy lead frame strips and releasing tablets used in a mold releasing agent treatment process are automatically supplied to the molding apparatus in a mold releasing agent treatment mode or a mold cleaning mode. After the mold releasing agent treatment mode or mold cleaning mode is complete, the molding apparatus is switched back to a normal molding process and normal lead frame strips and molding compound tablets are to the mold part. In addition, a pick-up part and a stack magazine part are designed to distinguish by-products generated during the mold releasing agent treatment process from normally molded products by switching from a normal molding process to either a mold releasing agent treatment process or a mold cleaning process.

Abstract translation: 提供了一种用于模制使用模塑料的半导体器件的成型设备，其中模具被脱模剂自动处理。 引线框条盒内部片剂和片剂装载部分被设计成使得在脱模剂处理过程中使用的虚拟引线框带和释放片在脱模剂处理模式或模具清洁中被自动提供给模制设备 模式。 在脱模剂处理模式或模具清洁模式完成之后，将成型装置切换回正常的成型工艺，并将正常的引线框条和模塑复合片放置在模具部分。 此外，拾取部分和堆叠盒部分被设计成将脱模剂处理过程中产生的副产物与正常模制产品相区分，从正常模塑过程切换到脱模剂处理工艺或模具 清洗过程。

公开(公告)号：US06956769B2

公开(公告)日：2005-10-18

申请号：US10373410

申请日：2003-02-24

Applicant: Sung-Soo Lee

Inventor： Sung-Soo Lee

IPC: G11C16/04 ,  G06F12/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/88 ,  G11C29/808 ,  G11C29/82

Abstract: A semiconductor memory device including an array with a first memory cell block having redundancy blocks and a second memory cell block having normal blocks. A redundancy block in the first memory cell block is substituted for a defective normal block in the second memory cell block. The substitution is performed by a block selection circuit. When substitution is required, the block selection circuit selects from among the first memory cell blocks in inverse order, beginning with the first memory cell block having the highest address. First memory cell blocks that are not substituted for defective cell blocks are used as normal memory cell blocks by the block selection circuit.

Abstract translation: 一种半导体存储器件，包括具有具有冗余块的第一存储单元块的阵列和具有正常块的第二存储单元块。 第一存储单元块中的冗余块代替第二存储器单元块中的有缺陷的正常块。 替代由块选择电路执行。 当需要替换时，块选择电路从第一存储单元块中以与地址最高的第一存储器单元块相反的顺序选择。 通过块选择电路将不替代缺陷单元块的第一存储单元块用作正常存储单元块。

公开(公告)号：US06380992B1

公开(公告)日：2002-04-30

申请号：US09276446

申请日：1999-03-25

Applicant: Sung Soo Lee

Inventor： Sung Soo Lee

IPC: G02F11345

CPC classification number: G02F1/1309 ,  G02F2001/136263

Abstract: A method for forming a defective pad repair structure in a liquid crystal display device having a plurality of pads disposed on a substrate. At least one defective pad repair line is provided to oppose the pads with an insulating layer disposed between the pads and the defective pad repair line. When at least one of the pads is broken, the broken pad can be restored by connecting the broken pad to the repair line by a welding process.

Abstract translation: 一种用于在具有设置在基板上的多个焊盘的液晶显示装置中形成有缺陷的焊盘修复结构的方法。 提供至少一个有缺陷的焊盘修补线以与焊盘相对，该绝缘层设置在焊盘和有缺陷的焊盘修补线之间。 当至少一个焊盘断裂时，可以通过焊接工艺将损坏的焊盘连接到修理线上来恢复破损的焊盘。

公开(公告)号：US06294885B1

公开(公告)日：2001-09-25

申请号：US09500605

申请日：2000-02-09

Applicant: Sung-Soo Lee ,  Jae-Ho Lee

Inventor： Sung-Soo Lee ,  Jae-Ho Lee

IPC: H01J3126

CPC classification number: H04N9/24 ,  H01J31/20 ,  H01J2231/121

Abstract: Disclosed is a display device having a beam index type color CRT that includes an index signal controller for controlling input and output of index signals, an index memory for temporally saving the index signals in units corresponding to of a screened image of a scene on a screen panel, and a switch for switching the index signals that is under the control of the index signal controller.

Abstract translation: 公开了一种具有光束折射型彩色CRT的显示装置，其包括用于控制索引信号的输入和输出的索引信号控制器，用于在与屏幕上的场景的屏幕图像相对应的单位中暂时保存索引信号的索引存储器 面板，以及用于切换在索引信号控制器的控制下的索引信号的开关。

公开(公告)号：US06184948B2

公开(公告)日：2001-02-06

申请号：US09005587

申请日：1998-01-12

Applicant: Sung Soo Lee

Inventor： Sung Soo Lee

IPC: G02F11333

CPC classification number: G02F1/13458 ,  G02F1/136286 ,  G02F2001/136254

Abstract: A method for manufacturing a liquid crystal display device on a substrate including the steps of forming a gate electrode, a gate line, a gate pad, a source pad, a first gate shorting bar, and a first source shorting bar using a first metal; forming a gate insulation layer, a semiconductor layer, and a doped semiconductor layer by sequentially depositing an insulation material, an intrinsic semiconductor material, and a doped semiconductor material, respectively; and forming a source electrode, a source line, a drain electrode, a second gate shorting bar, and a second source shorting bar using a second metal.

Abstract translation: 一种在基板上制造液晶显示装置的方法，包括以下步骤：使用第一金属形成栅极，栅极线，栅极焊盘，源极焊盘，第一栅极短路棒和第一源极短路棒; 通过分别依次沉积绝缘材料，本征半导体材料和掺杂半导体材料来形成栅绝缘层，半导体层和掺杂半导体层; 以及使用第二金属形成源电极，源极线，漏电极，第二栅极短路棒和第二源极短路棒。

公开(公告)号：US5712818A

公开(公告)日：1998-01-27

申请号：US537615

申请日：1995-10-02

Applicant: Sung-Soo Lee ,  Jin-Ki Kim

Inventor： Sung-Soo Lee ,  Jin-Ki Kim

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10

Abstract: The present invention provides a nonvolatile semiconductor memory comprising a plurality of floating gate-type memory cells arranged in a matrix form of rows and columns; a plurality of bit lines connected the memory cells arranged in the direction of said column; a plurality of data lines respectively connected to the plurality of bit lines; a plurality of latch circuits respectively connected to said plurality of data lines; a preset unit for presetting the plurality of latch circuits to predetermined logic states during a presetting operation; a unit for loading data to selected ones of the plurality of latch circuits through data input/output terminals during a data loading operation after the presetting operation; and unit for programming to the memory cells arranged and erased in one selected row, data loaded to the latch circuits of the selected portion and data presetted to remaining latch circuits except for the latch circuits of the selected portion during a programming operation after the data loading operation.

Abstract translation: 本发明提供了一种非易失性半导体存储器，包括以行和列的矩阵形式布置的多个浮动栅型存储单元; 连接沿所述列方向布置的存储单元的多个位线; 分别连接到所述多个位线的多条数据线; 分别连接到所述多条数据线的多个锁存电路; 预置单元，用于在预设操作期间将所述多个锁存电路预置到预定的逻辑状态; 用于在预置操作之后的数据加载操作期间通过数据输入/输出端将数据加载到多个锁存电路中的选定数据的单元; 以及用于编程的单元，用于在一个选定行中被布置和擦除的存储器单元，加载到所选部分的锁存电路的数据以及在数据加载之后的编程操作期间被预设给除了所选部分的锁存电路之外的剩余锁存电路的数据 操作。

公开(公告)号：US5684303A

公开(公告)日：1997-11-04

申请号：US708773

申请日：1996-09-05

Applicant: Tae-ho Kim ,  Sung-soo Lee

Inventor： Tae-ho Kim ,  Sung-soo Lee

IPC: G01J1/02 ,  G01J1/42 ,  G01J5/02 ,  G01J5/34 ,  G01J5/10

CPC classification number: G01J5/34

Abstract: A pyroelectric infrared radiation detector is capable of removing internal noise generated in a pyroelectric element as well as noise due to a power source in the manner that the induction noise of exterior high-frequency noise due to an inductance component in an outer lead wire is removed by connecting a second filter to a drain electrode of a FET, and the high-frequency interior noise is removed by installing a first filter between the pyroelectric element and FET. Therefore, a body sensing signal can be obtained by using only one pyroelectric element.

Abstract translation: 热电式红外线辐射检测器能够消除热电元件产生的内部噪声以及由于电源引起的噪声，使得外部引线中的电感成分引起的外部高频噪声的感应噪声被去除 通过将第二滤波器连接到FET的漏电极，并且通过在热电元件和FET之间安装第一滤波器来去除高频内部噪声。 因此，通过仅使用一个热电元件可以获得身体感测信号。