公开(公告)号：US08107304B2

公开(公告)日：2012-01-31

申请号：US12642414

申请日：2009-12-18

申请人： Todd A. Merritt ,  Troy A. Manning

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

摘要翻译： 地址选通锁存第一个地址。 突发周期会在内部增加地址选通信号。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。 控制线转换终止访问并初始化另一个突发访问。 写周期时间最大化，从而允许突发模式工作频率的增加。 读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。 通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。 对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

公开(公告)号：US20080259696A1

公开(公告)日：2008-10-23

申请号：US12144446

申请日：2008-06-23

申请人： Todd A. Merritt ,  Troy A. Manning

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

摘要翻译： 地址选通锁存第一个地址。 突发周期会在内部增加地址选通信号。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。 控制线转换终止访问并初始化另一个突发访问。 写周期时间最大化，从而允许突发模式工作频率的增加。 读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。 通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。 对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

公开(公告)号：US07373575B2

公开(公告)日：2008-05-13

申请号：US11393265

申请日：2006-03-29

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G01R31/28

CPC分类号： G11C29/022 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/20 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAM.

摘要翻译： 为具有已知序列的一系列应用数据信号产生预期数据信号，以确定数据信号组是否被适当地捕获。 捕获应用数据信号的第一组，并从捕获的第一组生成一组期望数据信号。 然后当第二组对应于期望数据信号组时，捕获并确定第二组应用数据信号以被适当地捕获。 以这种方式，当捕获的一系列数据信号从期望的捕获点在时间上移动时，将后续捕获的数据信号与其正确的预期数据信号进行比较，以便确定该组虽然在时间上移动仍然被正确捕获 。 模式发生器以这种方式生成期望数据信号，并且可以用于各种集成电路中，例如SLDRAM。

公开(公告)号：US07187190B2

公开(公告)日：2007-03-06

申请号：US11177892

申请日：2005-07-08

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G01R31/02 ,  G01R31/27

CPC分类号： G01R31/31905 ,  G01R31/2884 ,  G06F11/2733

摘要： An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operations of the integrated device. In order to test the relevant internal circuitry, a voltage is applied to a Test Mode Enable bond pad, overcoming the bias that grounds the redundant bond pad. In addition, the signal from the Test Mode Enable bond pad serves to ground any transmission from the main bond pad. As a result, the redundant bond pad may be used to test the relevant internal circuitry given its accessible location in relation to the testing equipment.

摘要翻译： 如果用于该电路的主接合焊盘难以用测试设备访问，则集成设备包括用于访问内部电路的冗余接合焊盘。 来自冗余接合焊盘的信号在集成器件的正常操作期间被偏置到接地。 为了测试相关的内部电路，将一个电压施加到测试模式使能焊盘，克服接地冗余焊盘的偏压。 此外，来自测试模式使能接合焊盘的信号用于接地主接合焊盘的任何传输。 因此，冗余接合焊盘可用于测试相对于测试设备的可访问位置的相关内部电路。

公开(公告)号：US06914830B2

公开(公告)日：2005-07-05

申请号：US10231682

申请日：2002-08-29

申请人： Todd A. Merritt ,  Troy A. Manning

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/401

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

摘要翻译： 集成电路存储器件被设计为执行高速数据写入周期。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。 写周期时间最大化以允许突发模式工作频率的增加。 靠近读出放大器的本地逻辑门用于控制写入数据驱动器，以提供最大写入时间，而不会在输入/输出线路平衡周期期间交叉电流。 通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。 对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

公开(公告)号：US06647523B2

公开(公告)日：2003-11-11

申请号：US10268351

申请日：2002-10-09

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C2900

CPC分类号： G11C29/022 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/20 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the first group. A second group of the applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals to determine whether the group, although shifted in time, was nonetheless correctly captured. Expect data signals are generated in this manner and may be utilized in a variety of integrated circuits, such as an SLDRAM.

摘要翻译： 为具有已知序列的一系列应用数据信号产生预期的数据信号，以确定是否适当地捕获所应用的数据信号的组。 捕获应用数据信号的第一组，并且从第一组生成一组期望数据信号。 然后当第二组对应于期望数据信号组时，捕获并确定第二组应用数据信号以被适当地捕获。 以这种方式，当捕获的一系列数据信号从期望的捕获点在时间上移动时，将后续捕获的数据信号与其正确的预期数据信号进行比较，以确定该组虽然在时间上移位，但仍被正确地捕获。 期望的数据信号以这种方式产生并且可以用在各种集成电路中，例如SLDRAM。

公开(公告)号：US06552945B2

公开(公告)日：2003-04-22

申请号：US09768897

申请日：2001-01-23

申请人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

发明人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

IPC分类号： G11C704

CPC分类号： G11C7/04 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

摘要翻译： 一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将积分电路性能中最大温度的参数存储在集成电路中的比较电路中 通过在比较电路中选择性地吹入可熔设备。 可熔断器件可以是反熔丝。 因此，集成电路能够向集成电路外部的设备提供信号，以指示集成电路可能太热而无法正常工作。

公开(公告)号：US06542569B2

公开(公告)日：2003-04-01

申请号：US09803061

申请日：2001-03-08

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C1900

CPC分类号： G11C7/109 ,  G11C7/1078

摘要： A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word. The identifying latch is programmed with the unique identifying data during power-up by storing the identifying data responsive to an initialization command packet. The shift register includes shift register circuits that are specifically adapted to operate at very high speeds.

公开(公告)号：US06525971B2

公开(公告)日：2003-02-25

申请号：US09361795

申请日：1999-07-27

申请人： Todd A. Merritt ,  Troy A. Manning

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： G11C11401

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

公开(公告)号：US06522163B1

公开(公告)日：2003-02-18

申请号：US09578917

申请日：2000-05-25

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： H03K1901

CPC分类号： G11C19/38 ,  G11C7/1072 ,  G11C19/00

摘要： A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column. The balanced transfer gate circuit is operable to couple the first signal terminal to the second signal terminal in response to the clock signals. The transfer gates are selectively clocked or activated such that the switching speed is independent of the order in which the individual series connected past transistors or transfer gates are activated. A shift register circuit, a memory device, and a computer system utilizing such a balanced switching circuit are also described.

摘要翻译： 平衡切换电路包括多个传输门，每个传输门具有输入端，输出端和适于接收控制信号的至少一个控制端。 可以由诸如n沟道和p沟道金属氧化物半导体（MOS）晶体管的传输晶体管组成的每个传输门可以响应于控制信号将输入端耦合到输出端。 多个传输门被布置成N行和N列，每行中的N个传输门的输入和输出端串联在第一信号端和第二信号端之间。 每个传输门的控制端连接到适于接收相应时钟信号的N个时钟端之一。 每个时钟端子耦合到每行仅一个传输门的控制端，每列中只有一个传输门。 平衡传输门电路可操作以响应于时钟信号将第一信号端耦合到第二信号端。 传输门被选择性地被定时或激活，使得开关速度独立于连接过去的晶体管或传输门的各个串联被激活的顺序。 还描述了移位寄存器电路，存储器件和利用这种平衡开关电路的计算机系统。