公开(公告)号：US08604548B2

公开(公告)日：2013-12-10

申请号：US13304086

申请日：2011-11-23

Applicant: Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括具有第二导电类型的第一导电类型，鳍状物，栅极，源极和漏极区域以及第二导电类型的第一掺杂区域的衬底。 在基板上形成多个隔离结构。 翅片设置在两个相邻隔离结构之间的基板上。 栅极设置在隔离结构上并覆盖翅片的一部分，其中由栅极覆盖的鳍的部分是第一导电类型。 源极和漏极区域在栅极的相应侧配置在鳍片中。 第一掺杂区域配置在源极和漏极区域下方的鳍片中，并与衬底相邻。 第一掺杂区的杂质浓度低于源区和漏区。

公开(公告)号：US20130302976A1

公开(公告)日：2013-11-14

申请号：US13471128

申请日：2012-05-14

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/283

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US08575708B2

公开(公告)日：2013-11-05

申请号：US13281448

申请日：2011-10-26

Applicant: Chien-Ting Lin

Inventor： Chien-Ting Lin

IPC: H01L29/02

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.

Abstract translation: 制造具有翅片结构的场效应晶体管的方法包括以下步骤。 提供了具有第一导电类型的离子阱的衬底，其中离子阱具有第一掺杂浓度。 至少形成设置在基板上的翅片结构。 至少进行第一离子注入以在衬底和沟道层之间形成具有第一导电类型的抗冲击掺杂区域，其中抗冲击掺杂区域具有高于第一掺杂浓度的第三掺杂浓度。 在执行第一离子注入之后，形成沿鳍片结构的至少一个表面设置的至少一个沟道层。 形成覆盖翅片结构的一部分的栅极。 形成在栅极旁边的翅片结构中设置的源极和漏极，其中源极和漏极具有第二导电类型。

公开(公告)号：US20130241003A1

公开(公告)日：2013-09-19

申请号：US13418367

申请日：2012-03-13

Applicant: Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract translation: 鳍状场效应晶体管工艺包括以下步骤。 提供基板。 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在基板上，其中第一鳍状场效应晶体管包括第一金属层和第二鳍状场效应晶体管 包括第二金属层。 对第一鳍状场效应晶体管进行处理处理，以调整第一鳍状场效应晶体管的阈值电压。 还提供了通过所述方法形成的鳍状场效应晶体管。

公开(公告)号：US20130105914A1

公开(公告)日：2013-05-02

申请号：US13281448

申请日：2011-10-26

Applicant: Chien-Ting Lin

Inventor： Chien-Ting Lin

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.

Abstract translation: 制造具有翅片结构的场效应晶体管的方法包括以下步骤。 提供了具有第一导电类型的离子阱的衬底，其中离子阱具有第一掺杂浓度。 至少形成设置在基板上的翅片结构。 至少进行第一离子注入以在衬底和沟道层之间形成具有第一导电类型的抗冲击掺杂区域，其中抗冲击掺杂区域具有高于第一掺杂浓度的第三掺杂浓度。 在执行第一离子注入之后，形成沿鳍片结构的至少一个表面设置的至少一个沟道层。 形成覆盖翅片结构的一部分的栅极。 形成在栅极旁边的翅片结构中设置的源极和漏极，其中源极和漏极具有第二导电类型。

公开(公告)号：US08278184B1

公开(公告)日：2012-10-02

申请号：US13287131

申请日：2011-11-02

Applicant: Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

Inventor： Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

IPC: H01L21/76

CPC classification number: H01L21/324 ,  H01L21/76224 ,  H01L21/823431

Abstract: A method of forming a non-planar transistor is provided. A substrate is provided. The substrate has a plurality of isolation regions to be formed and a plurality of fin regions to be formed. A first etching process is performed to form a plurality of first trenches having a first depth in the substrate within the isolation regions. At least a doping region is formed in the substrate within the fin regions. A second etching process is performed to deepen the first depth to a second depth and a plurality of fin structures are formed in the substrate within the fin regions. Lastly, a gate is formed on the fin structures.

Abstract translation: 提供了一种形成非平面晶体管的方法。 提供基板。 基板具有要形成的多个隔离区域和要形成的多个翅片区域。 执行第一蚀刻工艺以形成在隔离区域内的衬底中具有第一深度的多个第一沟槽。 至少在鳍片区域内的衬底中形成掺杂区域。 执行第二蚀刻处理以将第一深度加深到第二深度，并且在鳍片区域内的衬底中形成多个鳍结构。 最后，在翅片结构上形成一个浇口。

公开(公告)号：US20120142157A1

公开(公告)日：2012-06-07

申请号：US12961518

申请日：2010-12-07

Applicant: Cheng-Guo Chen ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Cheng-Hsien Chou

Inventor： Cheng-Guo Chen ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Cheng-Hsien Chou

IPC: H01L21/336 ,  H01L21/302

CPC classification number: H01L21/31053 ,  H01L29/66545

Abstract: The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.

Abstract translation: 根据本发明的制造半导体结构的方法包括平面化层间电介质层和硬掩模以在厚度方向上去除一部分硬掩模。 剩余的硬掩模的厚度小于硬掩模的原始厚度。 剩余的硬掩模和伪栅被去除以形成凹部。 在栅极材料填充到凹部中之后，可以获得具有相对精确的高度的栅极。

公开(公告)号：US20110014773A1

公开(公告)日：2011-01-20

申请号：US12890725

申请日：2010-09-27

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/28 ,  H01L21/762

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹部; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US20100320544A1

公开(公告)日：2010-12-23

申请号：US12488592

申请日：2009-06-22

Applicant: Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

Inventor： Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/77

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L28/20

Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管和电阻器的方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底中形成浅沟槽隔离; 在电阻区域的浅沟槽隔离中形成一个槽; 在所述晶体管区域中形成至少一个栅极和在所述电阻器区域的所述槽中形成电阻器; 并将栅极变换为金属栅极晶体管。

公开(公告)号：US07799630B2

公开(公告)日：2010-09-21

申请号：US12018214

申请日：2008-01-23

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

Abstract translation: 一种用于制造具有双金属栅极的CMOS器件的方法包括：提供具有不同导电类型的至少两个晶体管的衬底和覆盖两个晶体管的电介质层，平坦化介电层以暴露两个晶体管的栅极导电层，形成图案化 阻挡层暴露导电型晶体管之一，执行第一蚀刻工艺以去除导电型晶体管的栅极的一部分，重整金属栅极，去除图案化阻挡层，执行第二蚀刻工艺以去除部分 另一导电型晶体管的栅极，以及金属栅极的重整。