公开(公告)号：US20120327714A1

公开(公告)日：2012-12-27

申请号：US13363014

申请日：2012-01-31

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04

CPC classification number: G11C5/02 ,  G11C13/0007 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11578

Abstract: Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells provide needed isolation from the memory cells.

Abstract translation: 各种实施例涉及缺乏选择线的3D存储器阵列和由源极线和位线之一以及存储器单元之间的选择线控制的器件。 源极线和位线之间的二极管，并且存储器单元提供与存储器单元需要的隔离。

公开(公告)号：US20120168955A1

公开(公告)日：2012-07-05

申请号：US12983832

申请日：2011-01-03

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/538 ,  H01L21/3205

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L27/11565 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract translation: 集成电路图案包括具有X和Y方向部分的一组材料线。 X和Y方向部分具有第一和第二间距，第二间距比第一间距大至少3倍。 X方向部分是平行的，并且Y方向部分是平行的。 Y方向部分的端部区域包括主线部分和偏移部分。 偏移部分包括与主线部分间隔开并电连接到主线部分的偏移元件。 偏移部分限定用于后续图案转印过程的接触区域。 为了在集成电路处理过程中使用的多重图形化方法提供用于随后的图案转印过程的接触区域。

公开(公告)号：US08119481B2

公开(公告)日：2012-02-21

申请号：US12881570

申请日：2010-09-14

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue ,  Chien-Wei Liao

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

公开(公告)号：US20110300682A1

公开(公告)日：2011-12-08

申请号：US13210202

申请日：2011-08-15

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract translation: 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US08072813B2

公开(公告)日：2011-12-06

申请号：US12715996

申请日：2010-03-02

Applicant: Hang-Ting Lue ,  Tzu Hsuan Hsu

Inventor： Hang-Ting Lue ,  Tzu Hsuan Hsu

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.

Abstract translation: 非易失性存储器具有执行编程操作的逻辑，其控制一系列编程偏置布置，以用数据对存储器阵列的至少一个选定存储单元进行编程。 一系列编程偏置布置包括对存储器单元的多组改变栅极电压值。

公开(公告)号：US20110241100A1

公开(公告)日：2011-10-06

申请号：US13162386

申请日：2011-06-16

Applicant: ERH-KUN LAI ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

Inventor： ERH-KUN LAI ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract translation: 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。 该器件可以配置为NAND操作。

公开(公告)号：US08030166B2

公开(公告)日：2011-10-04

申请号：US12912635

申请日：2010-10-26

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.

Abstract translation: 描述了电荷捕获存储器单元，其具有沿通道侧面的凹槽注入并且具有与沟道相同的导电类型，并且哪些种植体的掺杂浓度高于通道的中心区域。 这样可以有效地禁止在通道侧的电荷俘获结构中由鸟嘴或其他异常引起的不均匀电荷捕获区域中的通道。 可以使用与标准浅沟槽隔离工艺兼容的工艺来形成口袋植入物。

公开(公告)号：US08022489B2

公开(公告)日：2011-09-20

申请号：US11134155

申请日：2005-05-20

Applicant: Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

Inventor： Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC: H01L29/788 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112

CPC classification number: H01L27/115 ,  G11C16/0408 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/515

Abstract: An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.

Abstract translation: 空气隧道浮动栅极存储单元包括限定在衬底上的空气通道。 在空气隧道上定义第一多晶硅层（浮栅）。 氧化物层设置在第一多晶硅层上，使得氧化物层覆盖第一多晶硅层并限定空气通道的侧壁。 用作字线的第二多晶硅层被定义在氧化物层上。 还公开了一种制造空气通道浮动栅极存储单元的方法。 在衬底上形成牺牲层。 在牺牲层上形成第一多晶硅层。 在第一多晶硅层上沉积氧化物层，使得氧化物层覆盖第一多晶硅层并限定牺牲层的侧壁。 使用热磷酸（H 3 PO 4）浸渍来蚀刻掉牺牲层以形成空气通道。

公开(公告)号：US20100271878A1

公开(公告)日：2010-10-28

申请号：US12430817

申请日：2009-04-27

Applicant: Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

Inventor： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC: G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L29/665 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

Abstract translation: 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

公开(公告)号：US20100258913A1

公开(公告)日：2010-10-14

申请号：US12421071

申请日：2009-04-09

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/00 ,  H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568

Abstract: A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality of third transfer patterns is formed, wherein each of the third transfer patterns is in a gap between a first transfer pattern and a second transfer pattern adjacent to the first transfer pattern. A portion of the mask layer is then removed, using the first transfer patterns, the second transfer patterns and third transfer patterns as a mask, so as to form a patterned mask layer. Further, a portion of the target layer is removed using the patterned mask layer as a mask.

Abstract translation: 提供了图案化方法。 首先，在目标层上依次形成掩模层和多个第一转印图案。 此后，在第一传送图案之间的间隙中形成多个第二图案。 之后，形成多个第三传送图案，其中第三传送图案中的每一个处于与第一传送图案相邻的第一传送图案和第二传送图案之间的间隙中。 然后使用第一转印图案，第二转印图案和第三转印图案作为掩模去除掩模层的一部分，以形成图案化掩模层。 此外，使用图案化掩模层作为掩模去除目标层的一部分。