公开(公告)号：US20070228436A1

公开(公告)日：2007-10-04

申请号：US11638310

申请日：2006-12-12

申请人： Hermann Ruckerbauer ,  Holger Schroeter

发明人： Hermann Ruckerbauer ,  Holger Schroeter

IPC分类号： H01L29/94

CPC分类号： H01L25/105 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/107 ,  H01L2924/15192

摘要： An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate is coupled to the at least one second contact of the second semiconductor memory device through the first electrically conductive conductor track. A second electrically conductive conductor track is arranged in the flexible substrate.

摘要翻译： 半导体存储器件的布置包括第一半导体存储器件和第二半导体存储器件。 半导体存储器件的布置也具有柔性衬底。 第一导电导体轨道布置在柔性基板中。 柔性基板的至少一个第一接触件通过第一导电导体轨道耦合到第二半导体存储器件的至少一个第二接触件。 第二导电导体轨道布置在柔性基板中。

公开(公告)号：US20070096333A1

公开(公告)日：2007-05-03

申请号：US11263412

申请日：2005-10-31

申请人： Amir Motamedi ,  Hermann Ruckerbauer

发明人： Amir Motamedi ,  Hermann Ruckerbauer

IPC分类号： H01L23/52

CPC分类号： H01L25/0652 ,  H01L23/36 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/05599

摘要： A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

摘要翻译： 公开了一种多芯片封装和方法。 在一个实施例中，多芯片封装包括安装在由第一对半导体集成电路芯片和第二对半导体集成电路芯片组成的印刷电路板上的间隔开的半导体集成电路芯片中的至少四个。 第一对半导体集成电路芯片的芯片基本上平行布置，并且第二对的半导体集成电路芯片的芯片基本上堆叠在第一对半导体集成电路芯片的芯片上。

公开(公告)号：US20070079057A1

公开(公告)日：2007-04-05

申请号：US11239829

申请日：2005-09-30

申请人： Hermann Ruckerbauer ,  Peter Gregorius

发明人： Hermann Ruckerbauer ,  Peter Gregorius

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1684

摘要： A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.

摘要翻译： 公开了半导体存储器系统。 在一个实施例中，本发明的半导体存储器系统和存储器模块提供了缓冲器，其中存储器模块上的至少一个写入缓冲器芯片仅缓冲并将从存储器控制器写入的写数据，命令和地址信号注册到存储器 筹码 由于读取数据通过单向点对点读取数据线直接从每个存储器芯片写回存储器控制器，与全缓冲DIMM概念相比，本半导体存储器系统实现了低延迟。 由于读取数据只是单向的，所以可以实现高传输带宽。

公开(公告)号：US20070033351A1

公开(公告)日：2007-02-08

申请号：US11377473

申请日：2006-03-16

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G06F13/00

CPC分类号： G11C5/04

摘要： The invention describes a semiconductor memory module unit for P2P data interchange with a memory controller. Memory chips having different data widths can be arranged on the semiconductor memory module unit in such a way as to enable a tree-like branching by signal data transmission from a node-like memory chip to a plurality of downstream memory chips while retaining the data width.

摘要翻译： 本发明描述了一种用于与存储器控制器进行P2P数据交换的半导体存储器模块单元。 具有不同数据宽度的存储芯片可以以这样的方式被布置在半导体存储器模块单元上，使得能够通过从节点状存储器芯片到多个下游存储器芯片的信号数据传输而实现树状分支，同时保持数据宽度 。

公开(公告)号：US07078793B2

公开(公告)日：2006-07-18

申请号：US10927312

申请日：2004-08-27

申请人： Hermann Ruckerbauer ,  Srdjan Djordjevic

发明人： Hermann Ruckerbauer ,  Srdjan Djordjevic

IPC分类号： H01L23/02

CPC分类号： G11C5/063

摘要： A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

摘要翻译： 半导体存储器模块包括布线板，其中至少多个数据线运行在k位的相应宽度上，并且具有多个存储器排列，每个存储器级别在每种情况下具有n个存储器芯片，并且至少一个 信号驱动器/控制芯片（集线器），在每种情况下将存储器芯片从每个存储器级连接到信号驱动器/控制芯片（集线器）的k位宽数据线和每个情况下的四个或八个存储器排列被布置 沿着相关联的数据线分布在布线板的顶部和底部，以这样的方式运行：在操作中，负载沿着相应的数据线运行分布。

公开(公告)号：US07043653B2

公开(公告)日：2006-05-09

申请号：US10215228

申请日：2002-08-08

申请人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

发明人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

摘要翻译： 将接收信号的逻辑/存储器组件的内部时钟信号作为参考时钟发送到发送逻辑/存储器组件。 借助于参考时钟，产生发送逻辑/存储器部件的输出单元的传输时钟，使得发送的信号与该部件的内部时钟信号同步到达接收部件的接收单元。

公开(公告)号：US20050041516A1

公开(公告)日：2005-02-24

申请号：US10872427

申请日：2004-06-22

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G06F11/08 ,  G06F12/16 ,  G06F13/16 ,  G11C7/00 ,  G11C7/10

CPC分类号： G11C7/1018 ,  G06F13/1684

摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

公开(公告)号：US20090040861A1

公开(公告)日：2009-02-12

申请号：US12180814

申请日：2008-07-28

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C8/08 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C8/08

摘要： A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.

摘要翻译： 存储装置包括至少两个存储器件，每个存储器件包括至少一个存储体。 操作存储装置的方法包括接收由存储器控制器产生的行激活命令，其中行激活命令包括存储体地址。 该方法还包括基于行激活命令来激活存储器设备之一的存储体中的字线，其中存储体地址用于选择存储器件。

公开(公告)号：US07383416B2

公开(公告)日：2008-06-03

申请号：US11130412

申请日：2005-05-17

申请人： Peter Oeschay ,  Hermann Ruckerbauer

发明人： Peter Oeschay ,  Hermann Ruckerbauer

IPC分类号： G06F12/00

CPC分类号： G06F12/0676 ,  G11C5/066 ,  G11C8/12

摘要： A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.

摘要翻译： 一种用于设置具有沿着字节通道分配的存储器芯片数量的存储器模块中的等级地址的方法，包括：将字节通道的第一存储器芯片设置为具有第一等级地址，从第一级地址生成第二等级地址 并且将第二等级地址驱动到第二个存储器芯片。 或者，第一等级地址可以被驱动到第二存储器芯片，然后在该第二存储器芯片中产生第二等级地址。 此外，响应于驱动第二/第一等级地址，将第二存储器芯片设置为具有第二等级地址。 通过串行管理总线或命令地址总线发送电源后的上电序列，或命令信号可以用来启动等级的设置。 等级地址沿着字节通道被DQ线重新驱动到相邻的存储器芯片。

公开(公告)号：US20070057695A1

公开(公告)日：2007-03-15

申请号：US11226456

申请日：2005-09-15

申请人： Hermann Ruckerbauer ,  Peter Gregorius

发明人： Hermann Ruckerbauer ,  Peter Gregorius

IPC分类号： H03K19/0175

CPC分类号： G11C11/4096 ,  G06F13/4077 ,  G11C7/1066

摘要： A semiconductor memory chip includes a re-drive unit for re-driving electrical signals to at least one semiconductor memory chip connected thereto. The re-drive unit includes a direct line connection between two connecting nodes, i.e., one input terminal and one output terminal of the semiconductor memory chip.

摘要翻译： 半导体存储器芯片包括用于将电信号重新驱动到连接到其上的至少一个半导体存储器芯片的重新驱动单元。 重新驱动单元包括两个连接节点之间的直接线路连接，即半导体存储器芯片的一个输入端子和一个输出端子。