公开(公告)号：US20210305430A1

公开(公告)日：2021-09-30

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Stephen SNYDER ,  Biswajeet GUHA ,  William HSU ,  Urusa ALAAN ,  Tahir GHANI ,  Michael K. HARPER ,  Vivek THIRTHA ,  Shu ZHOU ,  Nitesh KUMAR

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20210210514A1

公开(公告)日：2021-07-08

申请号：US17187284

申请日：2021-02-26

Applicant: INTEL CORPORATION

Inventor： Martin D. GILES ,  Tahir GHANI

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

公开(公告)号：US20210202696A1

公开(公告)日：2021-07-01

申请号：US16727406

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Mauro KOBRINSKY ,  Patrick MORROW ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.

公开(公告)号：US20210202479A1

公开(公告)日：2021-07-01

申请号：US16727355

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US20210193836A1

公开(公告)日：2021-06-24

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Ayan KAR ,  Nicholas THOMSON ,  Benjamin ORR ,  Nathan JACK ,  Kalyan KOLLURU ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20210167210A1

公开(公告)日：2021-06-03

申请号：US16700826

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20210159339A1

公开(公告)日：2021-05-27

申请号：US17161534

申请日：2021-01-28

Applicant: Intel Corporation

Inventor： Anand S. MURTHY ,  Daniel Bourne AUBERTINE ,  Tahir GHANI ,  Abhijit Jayant PETHE

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

公开(公告)号：US20210143051A1

公开(公告)日：2021-05-13

申请号：US17151083

申请日：2021-01-15

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20210125866A1

公开(公告)日：2021-04-29

申请号：US17141157

申请日：2021-01-04

Applicant: Intel Corporation

Inventor： Oleg GOLONZKA ,  Swaminathan SIVAKUMAR ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20210098373A1

公开(公告)日：2021-04-01

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan G. ALZATE VINASCO ,  Chieh-Jen KU ,  Shem O. OGADHOH ,  Allen B. GARDINER ,  Blake C. LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.