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公开(公告)号:US08796045B2
公开(公告)日:2014-08-05
申请号:US13689102
申请日:2012-11-29
Applicant: International Business Machines Corporation
Inventor: Daniel C. Worledge
CPC classification number: H01L43/12 , G11C11/1675 , H01L27/222
Abstract: A method of forming a magnetic random access memory (MRAM) device includes forming at least one write line, forming a first insulating layer over the at least one write line and forming a heating line on the first insulating layer. The method includes forming at least one tunnel junction above the at least one write line, the at least one tunnel junction connected to the heating line, forming a second insulating layer on the heating line and forming heat current supply vias at each end of the current line. The method further includes forming heat current supply lines connected to each heat current supply via and forming at least one read line above the at least one tunnel junction and physically connected to the at least one tunnel junction.
Abstract translation: 形成磁随机存取存储器(MRAM)器件的方法包括:形成至少一条写入线,在所述至少一条写入线上形成第一绝缘层,并在所述第一绝缘层上形成加热线。 该方法包括在至少一个写入线上方形成至少一个隧道结,至少一个连接到加热线的隧道结,在加热线上形成第二绝缘层,并在电流的每一端形成热电流供应通孔 线。 该方法还包括形成连接到每个热电流供应通路的热电流供应管线,并且形成至少一个隧道结上方的至少一条读取线,并物理连接至该至少一个隧道结。
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公开(公告)号:US11569439B2
公开(公告)日:2023-01-31
申请号:US15791893
申请日:2017-10-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Daniel C. Worledge
Abstract: A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel.
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公开(公告)号:US11527707B2
公开(公告)日:2022-12-13
申请号:US16686542
申请日:2019-11-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Stephen L. Brown , Guohan Hu , Jonathan Z. Sun , Daniel C. Worledge
Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
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公开(公告)号:US11164615B2
公开(公告)日:2021-11-02
申请号:US15922333
申请日:2018-03-15
Applicant: International Business Machines Corporation
Inventor: Luqiao Liu , Jonathan Z. Sun , Daniel C. Worledge
Abstract: A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.
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105.
公开(公告)号:US10510390B2
公开(公告)日:2019-12-17
申请号:US15616297
申请日:2017-06-07
Inventor: Guohan Hu , Jeong-Heon Park , Daniel C. Worledge
Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
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106.
公开(公告)号:US20190244647A1
公开(公告)日:2019-08-08
申请号:US16386490
申请日:2019-04-17
Applicant: International Business Machines Corporation
Inventor: Guohan Hu , Daniel C. Worledge
CPC classification number: G11C11/161 , G11C11/1675 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.
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公开(公告)号:US10361361B2
公开(公告)日:2019-07-23
申请号:US15094064
申请日:2016-04-08
Inventor: Guohan Hu , Younghyun Kim , Daniel C. Worledge
Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
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公开(公告)号:US20190043547A1
公开(公告)日:2019-02-07
申请号:US15666236
申请日:2017-08-01
Applicant: International Business Machines Corporation
Inventor: John K. DeBrosse , Jonathan Z. Sun , Daniel C. Worledge
Abstract: Improved spin hall MRAM designs are provided that enable writing of all of the bits along a given word line together using a separate spin hall wire for each MTJ. In one aspect, a magnetic memory cell includes: a spin hall wire exclusive to the magnetic memory cell; an MTJ disposed on the spin hall wire, wherein the MTJ includes a fixed magnetic layer separated from a free magnetic layer by a tunnel barrier; and a pair of selection transistors connected to opposite ends of the spin hall wire. An MRAM device and method for operation thereof are also provided.
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公开(公告)号:US10170688B2
公开(公告)日:2019-01-01
申请号:US15609647
申请日:2017-05-31
Applicant: International Business Machines Corporation
Inventor: Anthony J. Annunziata , Joel D. Chudow , Daniel C. Worledge
Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
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公开(公告)号:US20180373589A1
公开(公告)日:2018-12-27
申请号:US15842692
申请日:2017-12-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: John K. DeBrosse , Daniel C. Worledge
CPC classification number: G06F11/1016 , G11C11/16 , G11C29/06 , G11C29/34 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/789 , G11C2029/0403 , G11C2029/4402 , H01L27/222 , H01L43/08 , H03M13/2764 , H04L1/0071
Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
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