公开(公告)号：US11038015B2

公开(公告)日：2021-06-15

申请号：US16662332

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu ,  Xin Miao

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/28 ,  H01L29/41 ,  H01L29/51

Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

公开(公告)号：US11004678B2

公开(公告)日：2021-05-11

申请号：US16667987

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US10991798B2

公开(公告)日：2021-04-27

申请号：US16252768

申请日：2019-01-21

Applicant: International Business Machines Corporation

Inventor： Wenyu Xu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/10 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423

Abstract: Embodiments of the invention are directed to a method of forming a nanosheet transistor. A non-limiting example of the method includes forming a nanosheet stack having alternating layers of channel nanosheets and sacrificial nanosheets, wherein each of the layers of channel nanosheets includes a first type of semiconductor material, and wherein each of the layers of sacrificial nanosheets includes a second type of semiconductor material. The layers of sacrificial nanosheets are removed from the nanosheet stack, and layers of replacement sacrificial nanosheets are formed in the spaces that were occupied by the sacrificial nanosheets. Each of the layers of replacement sacrificial nanosheets includes a first type of non-semiconductor material.

公开(公告)号：US10957783B2

公开(公告)日：2021-03-23

申请号：US16682604

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wenyu Xu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04 ,  H01L21/3105 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device including a vertical transistor includes etching a longitudinal end portion of a fin on a substrate to form a gap exposing the substrate, forming a top source/drain region, and forming, around a horizontal portion and a vertical portion of a bottom source/drain region disposed on the substrate, a contact wrapping in a region including a location where the longitudinal end portion of the fin was removed by the etching.

公开(公告)号：US10957693B2

公开(公告)日：2021-03-23

申请号：US16584813

申请日：2019-09-26

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165

Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.

公开(公告)号：US10930778B2

公开(公告)日：2021-02-23

申请号：US16157896

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Chen Zhang ,  Xin Miao ,  Wenyu Xu

IPC: H01L21/82 ,  H01L21/76 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49

Abstract: A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.

公开(公告)号：US10902910B2

公开(公告)日：2021-01-26

申请号：US16452429

申请日：2019-06-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Chen Zhang ,  Wenyu Xu

IPC: G11C13/00 ,  G11C7/18 ,  H01L45/00 ,  G11C8/14

Abstract: The present invention provides PCM devices with gradual SET and RESET characteristics. In one aspect, a method of forming a PCM computing device includes: forming word lines and an insulating hardmask cap on a substrate; forming a PCM material over the word lines, having a tapered thickness; and forming bit lines over the PCM material, the insulating hardmask cap, and the word lines, wherein the tapered thickness of the PCM material varies gradually between the word lines and the bit lines. The tapered thickness can be formed by depositing a non-conformal layer of the PCM material or by depositing a conformal layer and then tapering the PCM material using a directional etch. A PCM device is also provided.

公开(公告)号：US10886391B2

公开(公告)日：2021-01-05

申请号：US16431862

申请日：2019-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L29/10

Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.

公开(公告)号：US10833073B2

公开(公告)日：2020-11-10

申请号：US16584803

申请日：2019-09-26

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165

Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.

公开(公告)号：US20200312909A1

公开(公告)日：2020-10-01

申请号：US16366309

申请日：2019-03-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Richard A. Conti ,  RUILONG XIE ,  Kangguo Cheng

IPC: H01L27/24 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66 ,  H01L45/00

Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.