SEMICONDUCTOR DEVICE WITH ENHANCED STRESS BY GATES STRESS LINER
    101.
    发明申请
    SEMICONDUCTOR DEVICE WITH ENHANCED STRESS BY GATES STRESS LINER 审中-公开
    具有增强应力的半导体器件由盖茨应力衬片

    公开(公告)号:US20110042728A1

    公开(公告)日:2011-02-24

    申请号:US12542748

    申请日:2009-08-18

    摘要: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

    摘要翻译: 在一个实施例中,提供了一种用于在半导体器件中形成应力的方法。 半导体器件可以在衬底上包括栅极结构,其中栅极结构包括存在于栅极导体上的至少一个虚拟材料。 在半导体器件顶部形成保形电介质层,并且在保形电介质层上形成层间电介质层。 层间电介质层可以被平坦化以暴露在栅极结构顶部的保形电介质层的至少一部分,其中共形介电层的暴露部分可被去除以暴露栅极结构的上表面。 可以去除栅极结构的上表面以露出栅极导体。 然后可以在至少一个栅极导体上方形成应力诱导材料。

    FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION
    102.
    发明申请
    FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION 有权
    通过离子植入形成的FIN和FINFET

    公开(公告)号:US20100203732A1

    公开(公告)日:2010-08-12

    申请号:US12368561

    申请日:2009-02-10

    摘要: A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

    摘要翻译: 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模,其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后,进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分,其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分,以提供亚光刻尺寸的图案,并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

    Structure for planar SOI substrate with multiple orientations
    103.
    发明授权
    Structure for planar SOI substrate with multiple orientations 失效
    具有多个取向的平面SOI衬底的结构

    公开(公告)号:US07691482B2

    公开(公告)日:2010-04-06

    申请号:US11473835

    申请日:2006-06-23

    IPC分类号: B32B9/04 H01L27/12

    摘要: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

    摘要翻译: 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法,包括以下步骤:在单个取向层的顶部提供多个取向表面,所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域,其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面,直到第一器件区域的表面基本上与第二器件区域的表面共面。

    Smooth and vertical semiconductor fin structure
    104.
    发明申请
    Smooth and vertical semiconductor fin structure 有权
    平滑和垂直的半导体鳍结构

    公开(公告)号:US20100048027A1

    公开(公告)日:2010-02-25

    申请号:US12195691

    申请日:2008-08-21

    IPC分类号: H01L21/302

    摘要: A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.

    摘要翻译: 公开了一种半导体鳍片结构的处理方法。 该方法包括在含有氢同位素的环境中对翅片结构进行热退火。 在热退火步骤之后,鳍结构被蚀刻成晶体取向的自限制的方式。 取决于晶体取向的蚀刻可以选择为含有氢氧化铵(NH 4 OH)的水溶液。 完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。 翅片结构侧壁是{110}平面。

    FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION
    105.
    发明申请
    FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION 审中-公开
    具有门极电极边缘的场效应器件增强型电介质和制造方法

    公开(公告)号:US20100038705A1

    公开(公告)日:2010-02-18

    申请号:US12190109

    申请日:2008-08-12

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.

    摘要翻译: 半导体结构和用于制造半导体结构的方法在诸如场效应晶体管结构的场效应结构内的与栅电极相邻的间隔物之下提供底切。 可以完全或不完全地覆盖插入在间隔物和半导体衬底之间的区域的底切部被栅极电介质填充。 与栅极和半导体衬底相比,栅极电介质具有比间隔物和半导体衬底之间更大的厚度。 可以使用顺序替换栅极电介质和栅极电极法制造半导体结构。

    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH
    106.
    发明申请
    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH 失效
    具有自对准独立门控阀的门控方案

    公开(公告)号:US20090203200A1

    公开(公告)日:2009-08-13

    申请号:US12027444

    申请日:2008-02-07

    IPC分类号: H01L21/027

    摘要: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

    摘要翻译: 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件,例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时,施加第二掩模,从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁,从而提高半导体制造操作的产量。

    STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C
    108.
    发明申请
    STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
    用于制造SiGe和/或Si:C的栅极应力工程的散装硅和SOI MOS器件中的分离自由应力通道的结构和方法

    公开(公告)号:US20090149010A1

    公开(公告)日:2009-06-11

    申请号:US12352504

    申请日:2009-01-12

    IPC分类号: H01L21/18

    摘要: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

    摘要翻译: 公开了通过具有SiGe和/或Si:C的栅极应力工程的体硅和SOI(绝缘体上硅)CMOS(互补金属氧化物半导体)器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底,衬底上的栅极介电层,以及SiGe和/或Si:C的层叠栅极结构,其具有在SSi(应变Si)/ SiGe或SSi的界面处产生的应力 / Si:C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层,在第一应力膜层上的应变SiGe或应变Si:C的第二应力膜层,以及半导体或导体 p(聚)-Si在第二应力膜层上。

    FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS
    110.
    发明申请
    FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS 有权
    FINFET结构使用不同的门电介质材料和门电极材料

    公开(公告)号:US20090057765A1

    公开(公告)日:2009-03-05

    申请号:US11847573

    申请日:2007-08-30

    IPC分类号: H01L27/12 H01L21/336

    摘要: A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

    摘要翻译: 半导体结构包括第一finFET和第二finFET。 第一finFET和第二finFET可以包括n-finFET和p-finFET,以提供CMOS finFET结构。 在半导体结构内,以下至少一个:(1)第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或(2)第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。