摘要:
Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure.
摘要:
Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要:
A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
摘要:
An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.
摘要:
A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.
摘要:
A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
摘要:
A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
摘要:
A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.
摘要:
A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.
摘要:
A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.