公开(公告)号：US20140024181A1

公开(公告)日：2014-01-23

申请号：US13551054

申请日：2012-07-17

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

摘要翻译： 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US20140015014A1

公开(公告)日：2014-01-16

申请号：US13545224

申请日：2012-07-10

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28008 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7834 ,  H01L29/7848

摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

摘要翻译： 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。

公开(公告)号：US20140001554A1

公开(公告)日：2014-01-02

申请号：US13534407

申请日：2012-06-27

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  G06F17/50 ,  H01L27/12

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

公开(公告)号：US08617956B2

公开(公告)日：2013-12-31

申请号：US12859414

申请日：2010-08-19

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/36

CPC分类号： H01L29/0847 ,  H01L21/28114 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

公开(公告)号：US20130313643A1

公开(公告)日：2013-11-28

申请号：US13478154

申请日：2012-05-23

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

摘要翻译： 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

公开(公告)号：US20130292766A1

公开(公告)日：2013-11-07

申请号：US13463402

申请日：2012-05-03

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

摘要翻译： 提供了半导体集成电路，并且包括形成在半导体衬底上的第一场效应晶体管（FET）器件和第二FET器件。 第一FET器件提高了在第一高度生长的源极/漏极（RSD）结构。 第二FET器件具有在大于第一高度的第二高度处生长的RSD结构，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

公开(公告)号：US08552487B2

公开(公告)日：2013-10-08

申请号：US13568601

申请日：2012-08-07

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.

摘要翻译： 半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器 在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

公开(公告)号：US20130249002A1

公开(公告)日：2013-09-26

申请号：US13424447

申请日：2012-03-20

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

公开(公告)号：US08513723B2

公开(公告)日：2013-08-20

申请号：US12689743

申请日：2010-01-19

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L28/40

摘要： An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.

摘要翻译： 提供了一种集成电路，其包括完全耗尽的半导体器件和存在于半导体绝缘体（SOI））衬底上的电容器。 完全耗尽的半导体器件可以是finFET半导体器件或平面半导体器件。 在一个实施例中，集成电路包括具有第一器件区域和第二器件区域的衬底。 衬底的第一器件区域包括存在于掩埋绝缘层上的第一半导体层。 在第一器件区域中的掩埋绝缘层存在于衬底的第二半导体层上。 第二器件区域包括第二半导体层，但是第二器件区域中不存在第一半导体层和掩埋绝缘层。 第一器件区域包括完全耗尽的半导体器件。 电容器存在于第二器件区域中。

公开(公告)号：US08486776B2

公开(公告)日：2013-07-16

申请号：US12886881

申请日：2010-09-21

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Katherine L. Saenger

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L21/823807

摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

摘要翻译： 应变Si和应变SiGe绝缘体器件，制造方法和设计结构。 该方法包括在绝缘体上硅晶片上生长SiGe层。 该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。 该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。 该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。 该方法还包括从NFET区域去除SiGe层。 该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。