公开(公告)号：US6137142A

公开(公告)日：2000-10-24

申请号：US28472

申请日：1998-02-24

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L21/761 ,  H01L27/092 ,  H01L27/12 ,  H01L27/01 ,  H01L27/04

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L27/1203

摘要： To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

摘要翻译： 为了减少在轻掺杂的体材料中形成的轻掺杂阱之间的边界处的p-n结泄漏，在该结处注入高浓度区域。 高浓度区域含有相当高的掺杂剂水平，因此降低了在结处的耗尽区域的宽度。 耗尽区域的减小的宽度又减少了结漏电。

公开(公告)号：US6072217A

公开(公告)日：2000-06-06

申请号：US95551

申请日：1998-06-11

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L27/12

CPC分类号： H01L27/1203

摘要： To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

摘要翻译： 为了降低具有背栅阱的完全耗尽的SOI器件中的阈值电平，器件的沟道区由本征或伪本征半导体形成。 此外，在氧化物层下方形成多个阱结构或隔离区，以减少器件的背栅极阱之间的二极管结泄漏。

公开(公告)号：US5773863A

公开(公告)日：1998-06-30

申请号：US292513

申请日：1994-08-18

申请人： James B. Burr ,  Michael P. Brassington

发明人： James B. Burr ,  Michael P. Brassington

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/788 ,  H01L29/94

CPC分类号： H01L29/1083 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

摘要： An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channel region. The transistor further includes a gate region positioned on the surface of the substrate over the channel region, and a buried region of the first conductivity type is positioned within the well region and below the surface of the substrate. The buried region has a dopant concentration of the first conductivity type sufficiently high to slow the growth of source-drain depletion regions and diminish the likelihood of punch through. The buried region may take the form of a buried electrode region or a retrograde well in alternate embodiments. The device is characterized by a gate threshold voltage of at most about 150 mV which can be electrically adjusted using back biasing or floating gate techniques.

摘要翻译： 描述了需要低功率并且具有高性能的改进的结型晶体管。 晶体管包括衬底，第一导电类型的阱区和由沟道区分隔的第二导电类型的源区和漏区。 晶体管还包括位于沟道区域上的衬底表面上的栅极区域，并且第一导电类型的掩埋区域位于阱区域内并在衬底的表面下方。 掩埋区域具有足够高的第一导电类型的掺杂剂浓度，以减缓源 - 漏耗尽区的生长并减少穿通的可能性。 在替代实施例中，掩埋区域可以采取掩埋电极区域或逆行井的形式。 该器件的特征在于栅极阈值电压至多约150mV，其可以使用反向偏置或浮动栅极技术进行电气调节。

公开(公告)号：US5753958A

公开(公告)日：1998-05-19

申请号：US543485

申请日：1995-10-16

申请人： James B. Burr ,  Douglas Alan Laird

发明人： James B. Burr ,  Douglas Alan Laird

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66659 ,  H01L29/1087

摘要： An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

摘要翻译： 本文公开了具有不对称袋区域的可调阈值电压MOS器件。 口袋区域邻近装置的通道区域邻近源极或漏极之一。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 具有这样的口袋区域的MOS器件可以通过将电位直接施加到其口袋区域来调节其阈值电压。 该能力通过提供电耦合到口袋区域的接触或导电接头来实现。 这种“袖带”也电耦合到金属化线（器件外部），该金属化线可以保持在与设备反偏特定量所需的电位相对应的指定电位。

公开(公告)号：US20140033160A1

公开(公告)日：2014-01-30

申请号：US13741246

申请日：2013-01-14

申请人： David R. Ditzel ,  James B. Burr

发明人： David R. Ditzel ,  James B. Burr

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.

摘要翻译： 软件控制晶体管体偏置。 访问目标频率。 使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。 晶体管的主体基于主体偏置值被偏置，其中特性被增强。

公开(公告)号：US08222914B2

公开(公告)日：2012-07-17

申请号：US12547392

申请日：2009-08-25

申请人： Robert Paul Masleid ,  James B. Burr

发明人： Robert Paul Masleid ,  James B. Burr

IPC分类号： G01R31/26

CPC分类号： H03K19/0027 ,  G01R31/2621 ,  H03K2217/0018

摘要： Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

摘要翻译： 用于调整阈值电压的系统和方法。 测量集成电路的晶体管的阈值电压。 当施加到晶体管的体阱时，偏置电压校正阈值电压和晶体管的期望阈值电压之间的差异。 偏置电压被编码到集成电路上的非易失性存储器中。 非易失性存储器可以是数字和/或模拟的。

公开(公告)号：US08003471B2

公开(公告)日：2011-08-23

申请号：US12715262

申请日：2010-03-01

申请人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

发明人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/7833

摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

摘要翻译： 具有超陡逆行通道的升高源/漏源的系统和方法。 根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。 半导体器件还包括形成在表面下方深度的超陡逆行通道区域。 深度约为栅极氧化物厚度的十至三十倍。 根据一个实施例的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

公开(公告)号：US07996809B2

公开(公告)日：2011-08-09

申请号：US12033832

申请日：2008-02-19

申请人： David R. Ditzel ,  James B. Burr

发明人： David R. Ditzel ,  James B. Burr

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.

摘要翻译： 软件控制晶体管体偏置。 访问目标频率。 使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。 晶体管的主体基于主体偏置值被偏置，其中特性被增强。

公开(公告)号：US07941675B2

公开(公告)日：2011-05-10

申请号：US10334918

申请日：2002-12-31

申请人： James B. Burr ,  Andrew Read ,  Tom Stewart

发明人： James B. Burr ,  Andrew Read ,  Tom Stewart

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and system of adaptive power control. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

摘要翻译： 一种自适应功率控制的方法和系统。 特定集成电路的特性用于自适应地控制集成电路的功率。

公开(公告)号：US07747974B1

公开(公告)日：2010-06-29

申请号：US11649443

申请日：2007-01-03

申请人： James B. Burr ,  William N. Schnaitter

发明人： James B. Burr ,  William N. Schnaitter

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. The PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.

摘要翻译： 一种用于优化使用深n阱栅格结构的NFET和PFET的体偏置连接的方法和装置。 在支撑多个NFET和具有小于0.2微米的标称栅极长度的PFET的CMOS衬底的表面下方形成深n阱。 深n阱是具有规则的孔阵列的栅格结构，其在衬底的底部和NFET之间提供电连续性。 PFET位于与埋置的n阱栅格结构连续的表面n阱中。 栅极和n阱布局基于n阱中包含的PFET的功能进行。