公开(公告)号：US5753958A

公开(公告)日：1998-05-19

申请号：US543485

申请日：1995-10-16

申请人： James B. Burr ,  Douglas Alan Laird

发明人： James B. Burr ,  Douglas Alan Laird

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66659 ,  H01L29/1087

摘要： An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

摘要翻译： 本文公开了具有不对称袋区域的可调阈值电压MOS器件。 口袋区域邻近装置的通道区域邻近源极或漏极之一。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 具有这样的口袋区域的MOS器件可以通过将电位直接施加到其口袋区域来调节其阈值电压。 该能力通过提供电耦合到口袋区域的接触或导电接头来实现。 这种“袖带”也电耦合到金属化线（器件外部），该金属化线可以保持在与设备反偏特定量所需的电位相对应的指定电位。

公开(公告)号：US08633547B2

公开(公告)日：2014-01-21

申请号：US12140197

申请日：2008-06-16

申请人： Robert Masleid ,  James B. Burr ,  Michael Pelham

发明人： Robert Masleid ,  James B. Burr ,  Michael Pelham

IPC分类号： H01L29/76

CPC分类号： H01L23/535 ,  H01L23/52 ,  H01L23/585 ,  H01L27/0218 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.

摘要翻译： 体偏电压布线结构跨越间隙的结构。 在一个实施例中，结构由至少一根金属线构成。

公开(公告)号：US08298896B2

公开(公告)日：2012-10-30

申请号：US13214593

申请日：2011-08-22

申请人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

发明人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/7833

摘要： Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

摘要翻译： 描述了具有超陡逆行通道的升高源极/漏极的系统和方法。 根据第一实施例，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面之上的栅极氧化物。 半导体器件还包括形成在表面下方深度的超陡逆行通道区域。 深度约为栅极氧化物厚度的十至三十倍。 实施例可以提供比常规技术中可获得的阈值电压特性更理想的主体偏置电压。

公开(公告)号：US07949864B1

公开(公告)日：2011-05-24

申请号：US11238446

申请日：2005-09-28

申请人： Vjekoslav Svilan ,  James B. Burr

发明人： Vjekoslav Svilan ,  James B. Burr

IPC分类号： G06F1/32 ,  G06F1/24

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

摘要翻译： 平衡自适应体偏置控制的系统和方法。 根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。 访问对应于期望的动态条件的第一动态指示符。 访问集成电路的第二和第三动态指示器。 通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。 基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。

公开(公告)号：US20110086478A1

公开(公告)日：2011-04-14

申请号：US12968032

申请日：2010-12-14

申请人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

IPC分类号： H01L21/8238

CPC分类号： H03K19/0027 ,  H03K2217/0018

摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

公开(公告)号：US20100321098A1

公开(公告)日：2010-12-23

申请号：US12873062

申请日：2010-08-31

申请人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

IPC分类号： H03K3/01

CPC分类号： H01L21/823892 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L29/78

摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

公开(公告)号：US07786756B1

公开(公告)日：2010-08-31

申请号：US11241552

申请日：2005-09-30

申请人： Vjekoslav Svilan ,  Tien-Min Chen ,  Kleanthes G. Koniaris ,  James B. Burr

发明人： Vjekoslav Svilan ,  Tien-Min Chen ,  Kleanthes G. Koniaris ,  James B. Burr

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K3/00

CPC分类号： G06F1/3203 ,  G06F1/305 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.

摘要翻译： 抑制闭锁的系统和方法。 根据本发明的第一实施例，闭锁抑制系统包括用于将施加到半导体器件的主体端子的电压与参考电压进行比较的电压比较器。 电压比较器也用于控制选择性耦合机构。 选择性耦合机构用于将主体端子选择性地耦合到相应的电源。 闩锁抑制系统优选地独立于用于向身体终端施加电压的电压源。

公开(公告)号：US07765412B1

公开(公告)日：2010-07-27

申请号：US11540117

申请日：2006-09-29

申请人： James B. Burr ,  Kleanthes G. Koniaris

发明人： James B. Burr ,  Kleanthes G. Koniaris

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Methods and systems for operating a semiconductor device (e.g., a processor) are described. The device is operating at a first operating condition and device temperature. The first operating condition for the device can be dynamically changed to a second operating condition. The second operating condition is selected considering the design operating life of the device.

摘要翻译： 描述了用于操作半导体器件（例如，处理器）的方法和系统。 该设备在第一个操作条件和设备温度下运行。 设备的第一个操作条件可以动态地更改为第二个操作条件。 考虑到设备的设计使用寿命，选择第二个操作条件。

公开(公告)号：US20100097092A1

公开(公告)日：2010-04-22

申请号：US12651244

申请日：2009-12-31

申请人： Kleanthes G. Koniaris ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  James B. Burr

IPC分类号： G01R31/28

CPC分类号： H03K3/012 ,  G01R31/2621 ,  G05B13/021 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03K3/0315 ,  Y02D10/126 ,  Y02D10/172

摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.

摘要翻译： 集成电路闭环反馈控制系统与方法。 在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。 基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。

公开(公告)号：US20100072575A1

公开(公告)日：2010-03-25

申请号：US12628011

申请日：2009-11-30

申请人： Mike Pelham ,  James B. Burr

发明人： Mike Pelham ,  James B. Burr

IPC分类号： H01L29/06

CPC分类号： H01L29/0646 ,  G11C5/146 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/0203 ,  H01L27/0222 ,  H01L27/0928 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

摘要： Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.

摘要翻译： 提供并描述了深阱区域的布局图案，以便于在半导体器件中布置体偏置电压。 布局图案包括对角子表面网格结构，轴向子表面网格结构，对角子表面条带结构和轴向子表面条带结构。 根据几个因素，为半导体器件的区域选择特定的布局图案。