公开(公告)号：US20140225264A1

公开(公告)日：2014-08-14

申请号：US14258476

申请日：2014-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej Sandhu ,  Scott Sills

IPC: H01L23/528

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract translation: 集成电路和形成方法提供形成在至少一个线性延伸导线的成角度端的接触区域。 在一个实施例中，具有接触着陆焊盘的导电线通过在掩模材料中图案化线形成，切割至少一条材料线以相对于材料线的延伸方向形成一角度，从所述材料线的成角度的端面形成延伸部 掩模材料，并通过使用所述材料线和延伸作为掩模进行蚀刻来图案化下面的导体。 在另一个实施例中，至少一条导线相对于导线的延伸方向以一定角度被切割，以产生成角度的端面，并且电接触着陆垫形成为与成角度的端面接触。

公开(公告)号：US20140166972A1

公开(公告)日：2014-06-19

申请号：US14185094

申请日：2014-02-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Neil Greeley ,  Gurtej Sandhu ,  John Smythe ,  Bhaskar Srinivasan

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract translation: 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US20140126854A1

公开(公告)日：2014-05-08

申请号：US14153342

申请日：2014-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Roy Meade ,  Gurtej Sandhu

IPC: G02F1/035

CPC classification number: H04B10/516 ,  G02B6/12007 ,  G02B6/122 ,  G02B6/29343 ,  G02F1/035 ,  G02F1/2252

Abstract: An optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide includes a plurality of modulator circuits configured along an optical transmission channel. Each modulator circuit includes at least one resonant structure that resonates at the first frequency when the modulator circuit that includes the at least one resonant structure is at a resonant temperature. Each modulator circuit has a different resonant temperature.

Abstract translation: 一种光波导，用于以第一频率传输输入到光波导的光信号。 光波导包括沿着光传输通道配置的多个调制器电路。 每个调制器电路包括当包括至少一个谐振结构的调制器电路处于共振温度时以第一频率谐振的至少一个谐振结构。 每个调制器电路具有不同的谐振温度。

公开(公告)号：US08703396B2

公开(公告)日：2014-04-22

申请号：US13710729

申请日：2012-12-11

Applicant: Micron Technology, Inc.

Inventor： Scott Sllls ,  Gurtej Sandhu ,  John Smythe ,  Ming Zhang

IPC: G03F7/26

CPC classification number: H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

Abstract translation: 一些实施例包括形成开口图案的方法。 所述方法可以包括在衬底上形成间隔的特征。 特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。 第一材料可以沿着特征的顶部和侧壁形成。 第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。 在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。 然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

公开(公告)号：US20140094026A1

公开(公告)日：2014-04-03

申请号：US14096052

申请日：2013-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej Sandhu ,  Scott Sills

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

公开(公告)号：US08629051B2

公开(公告)日：2014-01-14

申请号：US13751781

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu ,  Scott Sills

IPC: H01L21/44

CPC classification number: H01L27/10885 ,  H01L21/28008 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/06138 ,  H01L2924/12044

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

公开(公告)号：US08617958B2

公开(公告)日：2013-12-31

申请号：US13685402

申请日：2012-11-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej Sandhu ,  Bhaskar Srinivasan

IPC: H01L21/8222

CPC classification number: H01L21/04 ,  H01L27/1021 ,  H01L27/2418 ,  H01L29/1606 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract translation: 一些实施例包括形成二极管的方法。 可以在第一导电材料上形成堆叠。 堆叠可以按升序包括牺牲材料，至少一种电介质材料和第二导电材料。 间隔物可以沿着堆叠的相对侧壁形成，然后可以去除整个牺牲材料以在第一导电材料和至少一个电介质材料之间留下间隙。 在形成二极管的一些实施例中，可以在第一导电材料上形成层，其中包含支撑体的层散布在牺牲材料中。 可以在该层上形成至少一种介电材料，并且可以在该至少一种电介质材料的上方形成第二导电材料。 然后可以去除整个牺牲材料。

公开(公告)号：US20130234091A1

公开(公告)日：2013-09-12

申请号：US13837736

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Neil Greeley ,  Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC: H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1683

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract translation: 用于形成包含掺杂的硫族化物材料的存储器存取装置的自对准制造方法。 该方法可用于形成三维堆叠的交叉点存储器阵列。 该方法包括在第一导电电极上形成绝缘材料，图案化绝缘材料以形成暴露第一导电电极的部分的通孔，在绝缘材料的通孔内形成存储器访问装置，并在存储器访问上形成存储元件 设备，其中存储在所述存储器元件中的数据可经由所述存储器访问设备访问。 存储器存取装置由掺杂的硫族化物材料形成，并使用自对准制造方法形成。

公开(公告)号：US20130126997A1

公开(公告)日：2013-05-23

申请号：US13746206

申请日：2013-01-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: H01L43/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.