公开(公告)号：US11908814B2

公开(公告)日：2024-02-20

申请号：US17328134

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： John F. Kaeding ,  Owen R. Fay

IPC: H01L23/66 ,  H01Q1/22 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H10B12/00

CPC classification number: H01L23/66 ,  H01L23/5384 ,  H01L24/09 ,  H01L25/0657 ,  H01Q1/2283 ,  H10B12/00 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02372

Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.

公开(公告)号：US11848299B2

公开(公告)日：2023-12-19

申请号：US17971889

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Madison E. Wale ,  James L Voelz ,  Dylan W. Southern

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/13 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/4824 ,  H01L2224/48105 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1515 ,  H01L2924/182

Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

公开(公告)号：US11574820B2

公开(公告)日：2023-02-07

申请号：US16896043

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

公开(公告)号：US20230005904A1

公开(公告)日：2023-01-05

申请号：US17931284

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L25/18 ,  H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

公开(公告)号：US11456284B2

公开(公告)日：2022-09-27

申请号：US16939678

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Aparna U. Limaye ,  Owen R. Fay ,  Dong Soon Lim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

公开(公告)号：US11410981B2

公开(公告)日：2022-08-09

申请号：US17087043

申请日：2020-11-02

Applicant: Micron technology, inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

公开(公告)号：US20220094037A1

公开(公告)日：2022-03-24

申请号：US17543548

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/22 ,  H01L23/48 ,  H01L21/02

Abstract: Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

公开(公告)号：US11251516B2

公开(公告)日：2022-02-15

申请号：US16118670

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Owen R. Fay

IPC: H01Q1/22 ,  H01L23/00 ,  H04B1/38 ,  H01L23/66

Abstract: A semiconductor device, or semiconductor device package, that includes a substrate having an antenna structure on a surface of the substrate and a wire bond that electrically connects the antenna structure to the substrate to form an antenna or a first antenna configuration. The substrate may include a second antenna structure with the wire bond connected to the second antenna structure forming a second antenna or antenna configuration. The semiconductor device may include a radio communication device electrically connected to the substrate. The antenna or antenna configuration may be tuned to the requirements of the radio communication device. The antenna configuration may be tuned by connected to different antenna structures on the surface of the substrate. The antenna configuration may be tuned by changing a length of the wire bond, changing a diameter of the wire bond, and/or changing the material of the wire bond.

公开(公告)号：US20210367330A1

公开(公告)日：2021-11-25

申请号：US17392015

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/38 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525

Abstract: Systems and methods of manufacture are disclosed for semiconductor device assemblies having a front side metallurgy portion, a substrate layer adjacent to the front side metallurgy portion, a plurality of through-silicon-vias (TSVs) in the substrate layer, metallic conductors located within at least a portion of the plurality of TSVs, and at least one conductive connection circuitry between the metallic conductors and the front side metallurgy portion. The plurality of TSVs with metallic conductors located within are configured to form an antenna structure. Selectively breakable connective circuitry is used to form and/or tune the antenna structure.

公开(公告)号：US11171118B2

公开(公告)日：2021-11-09

申请号：US16503353

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors.