公开(公告)号：US10269430B2

公开(公告)日：2019-04-23

申请号：US15651985

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C16/04 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

公开(公告)号：US20180286879A1

公开(公告)日：2018-10-04

申请号：US16002129

申请日：2018-06-07

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US09941209B2

公开(公告)日：2018-04-10

申请号：US15068329

申请日：2016-03-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11517

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US09780107B2

公开(公告)日：2017-10-03

申请号：US14969709

申请日：2015-12-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto M. Meotto ,  Giulio Albini ,  Paolo Tessariol ,  Paola Bacciaglia ,  Marcello Mariani

IPC: H01L21/28 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/66833 ,  H01L29/792

Abstract: Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.

公开(公告)号：US20170200635A1

公开(公告)日：2017-07-13

申请号：US15471420

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US09627251B2

公开(公告)日：2017-04-18

申请号：US14722889

申请日：2015-05-27

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US09059261B2

公开(公告)日：2015-06-16

申请号：US14302160

申请日：2014-06-11

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成，随后可以与第一组横向的第二组平行条纹掩模形成。 例如，可以使用一组掩模来蚀刻介电层，以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后，该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。

公开(公告)号：US20140140134A1

公开(公告)日：2014-05-22

申请号：US14165072

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有一串存储器单元的装置和方法，导线和双极结型晶体管被配置为选择性地将该串存储器单元耦合到导线。 描述包括附加装置和方法的其它实施例。

公开(公告)号：US20130087849A1

公开(公告)日：2013-04-11

申请号：US13687726

申请日：2012-11-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto M. Meotto ,  Giulio Albini ,  Paolo Tessariol ,  Paola Bacciaglia ,  Marcello Mariani

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/66833 ,  H01L29/792

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.

Abstract translation: 本文公开的主题涉及一种制造半导体集成电路器件的方法，更具体地说，涉及一种制造电荷阱NAND快闪存储器件的方法。

公开(公告)号：US12190961B2

公开(公告)日：2025-01-07

申请号：US17988090

申请日：2022-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.