公开(公告)号：US11829729B2

公开(公告)日：2023-11-28

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

CPC classification number: G06F7/5443 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

公开(公告)号：US11803442B2

公开(公告)日：2023-10-31

申请号：US17943581

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  William A. Melton ,  Justin Eno

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0875

CPC classification number: G06F11/1068 ,  G06F12/0875 ,  G06F2212/1032

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

公开(公告)号：US11636893B2

公开(公告)日：2023-04-25

申请号：US17073621

申请日：2020-10-19

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

IPC: G11C11/40 ,  G11C11/4093 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/408

Abstract: An example memory sub-system includes: a plurality bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each bank group; and a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving, from a host, a command identifying a row buffer of the plurality of row buffers; and perform an operation with respect to the identified row buffer.

公开(公告)号：US20230051126A1

公开(公告)日：2023-02-16

申请号：US17885325

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Sean S. Eilert ,  Glen E. Hush ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F3/06 ,  G06F13/16

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

公开(公告)号：US20230050961A1

公开(公告)日：2023-02-16

申请号：US17885242

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kunal R. Parekh ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: G16B50/10 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G06F13/28

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.

公开(公告)号：US11556656B2

公开(公告)日：2023-01-17

申请号：US16582871

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06F21/60 ,  H03K19/21 ,  G06F21/79

Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

公开(公告)号：US11537861B2

公开(公告)日：2022-12-27

申请号：US16909632

申请日：2020-06-23

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/00 ,  G06N3/063 ,  G06F3/06 ,  G11C11/54 ,  H03M1/46 ,  G11C7/06 ,  G11C8/08 ,  G06N3/04

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US11494311B2

公开(公告)日：2022-11-08

申请号：US16573527

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean S. Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US11436071B2

公开(公告)日：2022-09-06

申请号：US16553731

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C5/06 ,  G06F11/07 ,  G06F11/10 ,  G11C15/04 ,  G11C11/409

Abstract: Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US11422748B2

公开(公告)日：2022-08-23

申请号：US17175911

申请日：2021-02-15

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.