公开(公告)号：US20150324261A1

公开(公告)日：2015-11-12

申请号：US14804027

申请日：2015-07-20

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G06F11/20 ,  G06F11/30 ,  G06F13/40

CPC classification number: G06F11/2005 ,  G06F11/1008 ,  G06F11/221 ,  G06F11/3027 ,  G06F11/3041 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4027

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

Abstract translation: 公开了编码技术的实现。 诸如数据总线反转（DBI）技术的编码技术可以在垂直堆叠的存储器模块中实现，但不限于此。 该模块可以是垂直堆叠的多个存储器集成电路，并且其通过在包括通晶片互连（TWI）的通道的一个实施例中形成的总线进行通信，但是不限于此。 一个这样的模块包括通常用于将总线上的数据信号重新路由到有缺陷的数据信道的备用通道。 在一个公开的技术中，查询备用信道的状态，并且如果一个或多个未被使用，则它们可以用于承载DBI位，从而允许总线的至少一部分根据 DBI算法。 根据重新路由所需的备用通道的位置和数量，可以通过各种方式在总线上分配DBI。 实现也可以与不包括DBI的其他编码技术一起使用。

公开(公告)号：US20140071771A1

公开(公告)日：2014-03-13

申请号：US14076985

申请日：2013-11-11

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C7/1003

Abstract: Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

Abstract translation: 显示了存储器件及其制作和操作方法。 所示的存储器件包括具有一个或多个缓冲管芯的堆叠存储器管芯。 在一个这样的存储器装置中，命令管芯通过一个或多个缓冲管芯与一个或多个下游存储器管芯通信。 一个或多个缓冲器管芯用于重复信号，并且可以潜在地提高堆叠中较高数量的存储器管芯的性能。

公开(公告)号：US20130235948A1

公开(公告)日：2013-09-12

申请号：US13865006

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: H04L25/49

CPC classification number: H04L25/4917 ,  H03K19/0002 ,  H04L25/4923 ,  H04L25/4927

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract translation: 公开了诸如涉及发射机电路的装置，其被配置为基于多个数字数字产生多电平信号。 一个这样的发射机电路包括信号输出和被配置为至少部分地基于多个数字数字提供控制信号的编码器。 发射机电路还包括被配置为接收一个或多个控制信号的第一组开关，并且选择性地对信号输出进行第一或第二电压基准。 发射机电路还包括分别提供第三和第四电压参考的第一和第二电压降电路。 第三和第四参考电压具有在第一和第二参考电压之间的电压电平。 发射机电路还包括被配置为接收一个或多个控制信号的第二组开关，并且选择性地将第三或第四电压基准传送到信号输出端。

公开(公告)号：US20130128994A1

公开(公告)日：2013-05-23

申请号：US13744236

申请日：2013-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: H04B15/00

CPC classification number: H04B15/00 ,  G09G5/006 ,  H04L25/0276

Abstract: Methods and apparatus are disclosed, such as those involving mixed-mode signaling that includes transmitting a differential signal and a common mode signals over the same pair of interconnect traces. One such apparatus includes a first transmitter configured to transmit a differential signal through a pair of electrically conductive lines in a first direction. The differential signal has a first frequency and carries electronic data. The apparatus further includes a second transmitter configured to transmit a common mode signal through the pair of electrically conductive lines in the first direction. The common mode signal is superimposed onto each of the differential signal. The common mode signal has a second frequency that is lower than the first frequency and carries a control signal. This configuration reduces the number of lines and pins on electronic circuits, thereby saving space thereon.

公开(公告)号：US12300597B2

公开(公告)日：2025-05-13

申请号：US18652515

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US12211580B2

公开(公告)日：2025-01-28

申请号：US17821604

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Shindeok Kang ,  Timothy M. Hollis

IPC: G11C7/10 ,  H03K7/02

Abstract: This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

公开(公告)号：US12189996B2

公开(公告)日：2025-01-07

申请号：US18490589

申请日：2023-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US20240268131A1

公开(公告)日：2024-08-08

申请号：US18404569

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Eric J. Stave

IPC: H10B80/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L2225/06534 ,  H01L2225/06541

Abstract: Methods, systems, and devices for near memory photonics are described. A memory device may include an optical interface, which may include an array of optical emitters and optical receivers, to convert between electrical signaling and optical signaling. For example, a vertical stack of memory dies may be coupled with an interface component which includes the optical interface. Optical signaling may be carried over one or more optical channels to a host device, and the host device may include an optical interface to convert the optical signaling back to electrical signaling. In some examples, the interface component may be positioned above the vertical stack of memory dies. Alternatively, the interface component may be positioned below the stack of memory dies, and may extend horizontally beyond the stack of memory dies, forming a porch section. In such cases, the optical interface may be distributed across the porch section.

公开(公告)号：US11894099B2

公开(公告)日：2024-02-06

申请号：US17562560

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US11862294B2

公开(公告)日：2024-01-02

申请号：US17936048

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C7/1063 ,  G11C7/222 ,  G11C8/06

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.